• Journal of Powder Materials
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• v.5 no.4
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• pp.250-257
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• 1998

The synthesis of titanium silicides ($Ti_3Si$, $TiSi_2$, $Ti_5Si_4$, $Ti_5Si_3$ and TiSi) by mechanical alloying has been investigated. Rapid, self-propagating high-temperature synthesis (SHS) reactions were observed to produce the last three phases during room-temperature high-energy ball milling of elemental powders. Such reactions appeared to be ignited by mechanical impact in an intimate, fine powder mixture formed after a critical milling period. During the high-energy ball milling, the repeated impact at contact points leads to a local concentration of energy which may ignite a self-propagating reaction. From in-situ thermal analysis, each critical milling period for the formation of $Ti_5Si_4$, $Ti_5Si_3$ and TiSi was observed to be 22, 35.5 and 53.5 min, respectively. $Ti_3Si$ and $TiSi_2$, however, have not been produced even till the milling period of 360 min due to lack of the homogeneity of the powder mixtures. The formation of titanium silicides by mechanical alloying and the relevant reaction rates appeared to depend upon the critical milling period, the homogeneity of the powder mixtures, and the heat of formation of the products involved.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.134-142
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• 1996

The epi-CoSi$_{2}$ layer was formed by alloying a Co(120$\AA$)/Ti(50$\AA$) bilayer. In addition, the ultra shallow p$^{+}$n junction of which depth is about not more than 40nm at the background concentration, 10$^{18}$atoms/cm$^{3}$ could be formed by annealing (RTA-II) the ion implanted epi-silicide. When the temperature of RTA-I is as low as possible and that of RTA-II is moderate, the p$^{+}$n junction that has low leakage current and stable epi-silicide layer could be obtained. That is, when th econdition of TRA-I was 900$^{\circ}C$/20sec and that of RTA-II was 900$^{\circ}C$/10sec, the reverse leakage current was as high as 11.3$\mu$A/cm$^{2}$ at -5V. The surface of CoSi$_{2}$ appeared considerably rough. However, when the conditon of RTA-I was 800$^{\circ}C$/20sec or 700$^{\circ}C$/20sec, the leakage currents were as low as 8.3nA/cm$^{2}$ and 9.3nA/cm$^{2}$, respectively and also the surfaces appeared very uniform.

• The Korean Journal of Ceramics
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• v.7 no.2
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• pp.70-73
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• 2001

Phase transformation of TiSi$_2$ confined in sub-micron area of which the size is around or smaller than the grain size of C49 TiSi$_2$ phase is studied. It has been known that the C49 to C54 phase change is massive transformation that occurs abruptly starting from C54 nuclei located at triple point grain boundaries of C49 phase. When the C49 phase is confined in sub-micron area, however, the massive phase transformation is observed to be hindered due to the lack of the triple point grain boundaries of C49 phase. Heat treatment at higher temperatures starts to decompose the C49 phase, and the resulting decomposed Ti atoms diffuse to, and react with, the underneath Si material to form C54 phase that exhibits spherical interface with silicon. The newly formed C54 grains can also trigger the massive phase transformation to convert the remaining undecomposed C49 grains to C54 grains by serving as nuclei like conventional C54 nuclei located at triple point grain boundaries.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.671-674
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• 2003

본 논문에서는 Cobalt interlayer 와 Titanium Nitride(TiN) capping layer를 Ni SALICIDE의 단점인 열 안정성과 sheet resistance 와 series 저항을 감소시키는데 적용하여 0.lum 급 CMOS 소자의 특성을 연구하였다. 첫째로, Ni/Si 의 interface 에 Co interlayer 를 증착하여 Nickel Silicide의 단점인 열 안정성 평가인 700℃, 30min의 furnace annealing 후에 낮은 sheet resistance와 누설전류를 줄일 수 있었다. 두번째로, TiN caping layer를 적용하여 실리사이드 형성시 산소와의 반응을 막아 실리사이드의 표면특성을 향상시켜 누설전류의 특성을 개선하였다. 결과적으로 소자의 구동전류 향상, 누설전류 저하, 낮은 면저항으로 소자의 특성을 개선하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.4
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• pp.261-265
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• 2011

This paper describes the fabrication and characteristics of a Au/Ni/Ti/3C-SiC Schottky diode with field plate (FP) edge termination. The Schottky contacts were annealed for 30 min at temperatures ranging from 0 to $800^{\circ}C$. At annealing temperature of $600^{\circ}C$, it showed an inhomogeneous Schottky barrier and had the best electrical characteristics. However, the annealing of $800^{\circ}C$ replaced it with ohmic behaviors because of the formation of many different types of nickel silicides. The fabricated Schottky diode had a breakdown voltage of 200 V, Schottky barrier height of 1.19 eV and worked normally even at $200^{\circ}C$.

• Korean Journal of Materials Research
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• v.4 no.1
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• pp.107-112
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• 1994

The phase transition and the surface and interface morphologies of $TiSi_2$ formed on atomically clean Si substrates are investigated. 200$\AA$ Ti and 400$\AA$ Si films on Si(ll1) have been codeposited at elevated temperatures (400~$800^{\circ}C$) in ultrahigh vacuum. The phase transition of TiSiL is characterized with using XRD. The results distinguish the formation of the C49 and C54 crystalline titanium silicides. The surface and interface morphologies of titanium silicides have been examined with SEM and TEM. A relatively smootb surface is observed for the C49 phase while a rough surface and interface are observed for C54 phase. The islanding of the C54 phase becomes severe at high temperature ($800^{\circ}C$). Islands of TiSiL have been observed at temperatures above $700^{\circ}C$ but no islands are observed at temperatures below $600^{\circ}C$. For films deposited at $400^{\circ}C$ and 500%. weak XRD peaks corresponding to TiSi were observed and TEM micrographs exhibited small crystalline regions of titanium silicide at the interface.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.237-240
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• 2002

In this W, a NiSi technology suitable for sub-100nm CMOS sevice is proposed. It seems that capping layer has little effect on the sheet resistance and junction leakage current when there is no thermal treatment. However, there happened agglomeration and drastic increase of Junction leakage current without capping layer. In other word, capping layer especially TiN capping layer is highly effective in suppressing thermal effect. It is shown that the sheet resistance of 0.12${\mu}{\textrm}{m}$ linewidth and shallow p+/n junction with NiSi were stable up to 700 t /30 minute thermal treatment.

• 연구논문집
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• s.31
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• pp.113-125
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• 2001

Silicon addition in titanium alloys generally results in solid solution hardening by silicon itself and precipitation hardening by titanium silicides. The morphology and distribution of the titanium silicides depend upon the alloy chemistry or the heat treatment condition, and play an important role in improving the mechanical properties of the alloys. In this study, the morphology and crystallographic characteristics of the titanium silicides in the Ti-Fe-Si alloy system were studied. Three types of silicides were found in the alloys; (1) interconnected chain-like silicides at grain boundary, (2) coarse silicides over im, (3) fine silicides smaller than 0.2m. Ti3Si was dominant in cast + HIP condition while Ti5Si3 was dominant in as-cast state. It is recognized that $Ti_5Si_3$$\rightarrow$$Ti_3Si$ transition occurred by the peritectoid reaction and it may be promoted by the pressure during HIP. However, in the case of the fine silicides, $Ti_3Si$ and $Ti_5Si_3$ were found simultaneously even after HIP. Such a fine silicide was found to have a crystallographic orientation relationship with matrix.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.603-606
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• 2005

In this paper, the formation and thermal stability of Ni-silicide using Ni-Pd alloys is studied for ultra shallow S/D junction of nano-scale CMOSFETs. There are no different effects when Ni-Pd is used in single structure and TiN capping structure. But, in case of Cobalt interlayer structure, it was found that Pure Ni had lower sheet resistance than Ni-Pd, because of a thick silicide. Also, Ni-Pd has merits that surface of silicide and interface between silicide and silicon have a good morphology characteristics. As a result, Ni-Pd is an optimal candidate for shallow S/D junction when cobalt is used for thermal stability.

• Electrical & Electronic Materials
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• v.4 no.4
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• pp.304-311
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• 1991

본 연구에서는 p형(100) 실리콘 기판 위에 LPCVD법으로 산화막과 다결정 실리콘을 증착하고 그 위에 Magnetron Sputtering법으로 티타늄을 500.angs.을 증착한 후, 열처리 온도 500-900.deg.C 사이에서 열처리 시간을 변화시키면서 N$_{2}$ 분위기 속에서 급속 열처리하여 티타늄 실리사이드를 형성하고 그 특성을 조사하였다. 500-600.deg.C 온도 범위에서 10초간 열처리한 시료에서는 실리사이드상은 나타나지 않고, 산소등의 불순물이 티타늄 박막 내로 확산되어 600.deg.C에서 면 저항이 최대값을 보였으며 열처리 온도는 675-750.deg.C로 높이자 TiSi상이 나타나면서 면저항이 감소되고 결정립의 크기가 크게 증가하였다. 또한 열처리온도 800.deg.C에서 나타나기 시작한 TiSi$_{2}$상은 열처리 온도 850.deg.C까지 TiSi상과 공존하면서 면저항과 reflectance는 계속 감소했다. 900.deg.C에서 10초간 열처리한 시료에서는 orthorhombic구조의 완전한 실리사이드 상만 나타났다. 최종적인 티타늄 실리사이드 박막의 두께는 1200.angs.이며 비저항은 18.mu..OMEGA.cm였다.