• Journal of Korea Port Economic Association
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• v.36 no.1
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• pp.41-58
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• 2020

This study aims to investigate the technical efficiency of major container ports in the Bay of Bengal area and to study how certain factors influence the efficiency of container ports and terminals. The research is conducted on the four main container ports in the Bay of Bengal area, namely, Colombo Port in Sri Lanka, Chennai Port in India, Chittagong Port in Bangladesh, and Yangon Port in Myanmar. There are three input variables (quay length, storage area, and the number of cranes) and two output variables (throughput twenty-foot equivalent units and vessel calls) chosen for the process in this study. This paper evaluates the efficiency score of the defined variables and suggests implications for further improvement of the core competitiveness of the four selected ports. The findings indicate that Colombo Port is the most efficient on a technical scale, followed by Chennai Port, Yangon Port, and Chittagong Port. However, the slack and radial movement calculation results show that the inputs and outputs of the four ports need to be adjusted to be efficient and to reduce the amount of resources that are wasted. The results validate the adaptability of the improved data envelopment analysis algorithm in port efficiency analysis. The research findings provide an overview of the efficiencies of the selected container ports and can potentially affect the port management decisions made by policymakers, terminal operators, and carriers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.29-38
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• 2009

In this paper, a high performance pipelined computing design of parallel multiplier-temporal buffer-parallel accumulator is present for the convolution-based non-cascaded architecture aiming at the real time Discrete Wavelet Transform(DWT) processing. The convolved multiplication of DWT would be reduced upto 1/4 by utilizing the filter coefficients symmetry and the up/down sampling; and it could be dealt with 3-5 times faster computation by LUT-based DA multiplication of multiple filter coefficients parallelized for product terms with an image data. Further, the reutilization of computed product terms could be achieved by storing in the temporal buffer, which yields the saving of computation as well as dynamic power by 50%. The convolved product terms of image data and filter coefficients are realigned and stored in the temporal buffer for the accumulated addition. Then, the buffer management of parallel aligned storage is carried out for the high speed sequential retrieval of parallel accumulations. The convolved computation is pipelined with parallel multiplier-temporal buffer-parallel accumulation in which the parallelization of temporal buffer and accumulator is optimize, with respect to the performance of parallel DA multiplier, to improve the pipelining performance. The proposed architecture is back-end designed with 0.18um library, which verifies the 30fps throughput of SVGA(800$\times$600) images at 90MHz.

• Journal of Advanced Navigation Technology
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• v.13 no.6
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• pp.916-925
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• 2009

4S (Ship to Ship, Ship to Shore) communication is the key to strategic development of e-navigation, a core element of IT vessel convergence. 4S communication is intended to integrate and standardize various communication infrastructures on land and communication equipment complying with communication equipment equipped in ships. This paper aims to apply the Korean technology IEEE 802.16e adopted as an international standard, to replace and compensate for existing vessel communication media such as low speed HF/MF/VHF to the ocean environment. To this end, various experimental conditions between the coast station where a relay station was installed and related equipment equipped on a ship are set. Communication signals were monitored and the RSSI and CINR were measured. Based on experimental analysis and results, various challenges and solutions which may occur in ocean environment were sought, and communication availability was analyzed through transmission data throughput, at the maximum effective distance range of the signal. It was proven that high speed multimedia data could be exchanged for up to 20 km even among 80km kph ships moving around near the sea, ensuring that this technology could be applied to the ocean environment.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.7
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• pp.429-439
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• 2006

A desktop grid, which is a computing grid composed of idle computing resources in a large network of desktop computers, is a promising platform for compute-intensive distributed computing applications. However, due to reliability and unpredictability of computing resources, effective scheduling of parallel computing applications on such a platform is a difficult problem. This paper proposes a new scheduling method aimed at reducing the total execution time of a parallel application on a desktop grid. The proposed method is based on utilizing the histories of execution behavior of individual computing nodes in the scheduling algorithm. In order to test out the feasibility of this idea, execution trace data were collected from a set of 40 desktop workstations over a period of seven weeks. Then, based on this data, the execution of several representative parallel applications were simulated using trace-driven simulation. The simulation results showed that the proposed method improves the execution time of the target applications significantly when compared to previous desktop grid scheduling methods. In addition, there were fewer instances of application suspension and failure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.71-80
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• 2007

This paper describes an efficient hardware design of WiBro security processor (WBSec) supporting for the security sub-layer of WiBro wireless internet system. The WBSec processor, which is based on AES (Advanced Encryption Standard) block cipher algorithm, performs data oncryption/decryption, authentication/integrity, and key encryption/decryption for packet data protection of wireless network. It carries out the modes of ECB, CTR, CBC, CCM and key wrap/unwrap with two AES cores working in parallel. In order to achieve an area-efficient implementation, two design techniques are considered; First, round transformation block within AES core is designed using a shared structure for encryption/decryption. Secondly, SubByte/InvSubByte blocks that require the largest hardware in AES core are implemented using field transformation technique. It results that the gate count of WBSec is reduced by about 25% compared with conventional LUT (Look-Up Table)-based design. The WBSec processor designed in Verilog-HDL has about 22,350 gates, and the estimated throughput is about 16-Mbps at key wrap mode and maximum 213-Mbps at CCM mode, thus it can be used for hardware design of WiBro security system.

• Journal of Korea Port Economic Association
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• v.32 no.2
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• pp.137-156
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• 2016

This study analyzes the optimal service levels of exclusive container terminals in terms of the optimal berth occupancy rate and the ships' waiting ratios, based on the number of berths. We develop a simulation model using berth throughput data from pier P, Busan New Port, a representative port in Korea, and apply the simulation results to different numbers of berths. In addition to the above results, we analyze the financial data and costs of delayed ships and delayed cargoes for the past three years from the viewpoints of the terminal operation company (TOC), shipping companies, and shippers to identify the optimal service level for berth occupancy rates that generate the highest net profit. The results show that the optimal levels in the container terminal are a 63.4% berth occupancy rate and 10.6% ship waiting ratio in berth 4,66.0% and 9.6% in berth 5, and 69.0% and 8.5% in berth 6. However, the results of the 2013 study by the Ministry of Maritime Affairs and Fisheries showed significantly different optimal service levels: a 57.1% berth occupancy rate and 7.4% ship waiting ratio in berth 4; 63.4% and 6.6% in berth 5; and 66.6% and 5.6% in berth 6. This suggests that optimal service level could change depending on when the analysis is performed. In other words, factors affecting the optimal service levels include exchange rates, revenue, cost per TEU, inventory cost per TEU, and the oil price. Thus, optimal service levels can never be fixed. Therefore, the optimal service levels for container terminals need to be able to change relatively quickly, depending on factors such as fluctuations in the economy, the oil price, and exchange rates.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.2
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• pp.37-43
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• 1999

Modules of the system that requires large capacity and high-speed information processing are implemented in the form of MCM that allows high-speed data processing, high density circuit integration and widely applied to such fields as ATM, GPS and PCS. Hence we developed the ATM switching module that is consisted of three chips and 2.48 Gbps data throughput, in the form of 10 multi-layer by Cu/Photo-BCB and 491pin PBGA which size is $48 \times 48 \textrm {mm}^2$. hnologies required for the development of the MCM includes extracting parameters for designing the substrate/package through the interconnect characterization to implement the high-speed characteristics, thermal management at the high-density MCM, and the generation of the testability that is one of the most difficult issues for developing the MCM. For the development of the ATM Switching MCM, we extracted signaling delay, via characteristics and crosstalk parameters through the interconnect characterization on the MCM-D. For the thermal management of 15.6 Watt under the high-density structure, we carried out the thermal analysis. formed 1.108 thermal vias through the substrate, and performed heat-proofing processing for the entire package so that it can keep the temperature less than $85^{\circ}C$. Lastly, in order to ensure the testability, we verified the substrate through fine pitch probing and applied the Boundary Scan Test (BST) for verifying the complex packaging/assembling processes, through which we developed an efficient and cost-effective product.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.22 no.6
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• pp.1-10
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• 2021

The interest in underwater acoustic sensor networks (UWASNs), along with the rapid development of underwater industries, has increased. To operate UWASNs efficiently, it is important to adopt well-designed medium access control (MAC) protocols that prevent collisions and allow the sharing of resources between nodes efficiently. On the other hand, underwater channels suffer from a narrow bandwidth, long propagation delay, and low data rate, so existing terrestrial node pairing schemes for non orthogonal multiple access (NOMA) cannot be applied directly to underwater environments. Therefore, a multi-dimensional node pairing scheme is proposed to consider the unique underwater channel in UWASNs. Conventional NOMA schemes have considered the channel quality only in node pairing. Unlike previous schemes, the proposed scheme considers the channel gain and many other features, such as node fairness, traffic load, and the age of data packets to find the best node-pair. In addition, the sender employs a list of candidates for node-pairs rather than path loss to reduce the computational complexity. The simulation results showed that the proposed scheme outperforms the conventional scheme by considering the fairness factor with 23.8% increases in throughput, 28% decreases in latency, and 5.7% improvements in fairness at best.

• The Journal of Korean Institute of Next Generation Computing
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• v.13 no.3
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• pp.72-83
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• 2017

GPUs can provide high throughput with latency hiding by executing many warps in parallel. MSHR(Miss Status Holding Registers) for L1 data cache tracks cache miss requests until required data is serviced from lower level memory. In recent GPUs, excessive requests for cache resources cause underutilization problem of GPU resources due to cache resource reservation fails. In this paper, we propose a new warp scheduling technique to reduce stall cycles under MSHR resource shortage. Cache miss rates for each warp is predicted based on the observation that each warp shows similar cache miss rates for long period. The warps showing low miss rates or computation-intensive warps are given high priority to be issued when MSHR is full status. Our proposal improves GPU performance by utilizing cache resource more efficiently based on cache miss rate prediction and monitoring the MSHR entries. According to our experimental results, reservation fail cycles can be reduced by 25.7% and IPC is increased by 6.2% with the proposed scheduling technique compared to loose round robin scheduler.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.5_6
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• pp.257-266
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• 2007

In On-Chip bus, the arbitration scheme is one of the critical factors that decide the overall system performance. The arbitration scheme used in traditional shared bus is the master-side arbitration based on the request and grant signals between multiple masters and single arbiter. In the case of the master-side arbitration, only one master and one slave can transfer the data at a time. Therefore the throughput of total bus system and the utilization of resources are decreased in the master-side arbitration. However in the slave-side arbitration, there is an arbiter at each slave port and the master just starts a transaction and waits for the slave response to proceed to the next transfer. Thus, the unit of arbitration can be a transaction or a transfer. Besides the throughput of total bus system and the utilization of resources are increased since the multiple masters can simultaneously perform transfers with independent slaves. In this paper, we implement and analyze the arbitration schemes for the Multi-Layer AHB BusMatrix based on the slave-side arbitration. We implement the slave-side arbitration schemes based on fixed priority, round robin and dynamic priority and accomplish the performance simulation to compare and analyze the performance of each arbitration scheme according to the characteristics of the master and slave. With the performance simulation, we observed that when there are few masters on critical path in a bus system, the arbitration scheme based on dynamic priority shows the maximum performance and in other cases, the arbitration scheme based on round robin shows the highest performance. In addition, the arbitration scheme with transaction based multiplexing shows higher performance than the same arbitration scheme with single transfer based switching in an application with frequent accesses to the long latency devices or memories such as SDRAM. The improvements of the arbitration scheme with transaction based multiplexing are 26%, 42% and 51%, respectively when the latency times of SDRAM are 1, 2 and 3 clock cycles.