• International Journal of Internet, Broadcasting and Communication
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• v.12 no.2
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• pp.30-36
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• 2020

We demonstrated a successful fabrication of 4" Gallium Nitride (GaN)/Diamond High Electron Mobility Transistors (HEMTs) incorporated with Inner Slot Via Hole process. We made in manufacturing technology of 4" GaN/Diamond HEMT wafers in a compound semiconductor foundry since reported [1]. Wafer thickness uniformity and wafer flatness of starting GaN/Diamond wafers have improved greatly, which contributed to improved processing yield. By optimizing Laser drilling techniques, we successfully demonstrated a through-substrate-via process, which is last hurdle in GaN/Diamond manufacturing technology. To fully exploit Diamond's superior thermal property for GaN HEMT devices, we include Aluminum Nitride (AlN) barrier in epitaxial layer structure, in addition to conventional Aluminum Gallium Nitride (AlGaN) barrier layer. The current collapse revealed very stable up to Vds = 90 V. The trapping behaviors were measured Emission Microscope (EMMI). The traps are located in interface between Silicon Nitride (SiN) passivation layer and GaN cap layer.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.3
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• pp.11-19
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• 2023

Recently with the rapid advancement of artificial intelligence (AI) technologies such as Chat GPT, AI semiconductors have become important. AI technologies require the ability to process large volumes of data quickly, as they perform tasks such as big data processing, deep learning, and algorithms. However, AI semiconductors encounter challenges with excessive power consumption and data bottlenecks during the processing of large-scale data. Thus, the latest packaging technologies are required for AI semiconductor computations. In this study, the authors have described packaging technologies applicable to AI semiconductors, including interposers, Through-Silicon-Via (TSV), bumping, Chiplet, and hybrid bonding. These technologies are expected to contribute to enhance the power efficiency and processing speed of AI semiconductors.

• Proceedings of the KWS Conference
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• 2010.05a
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• pp.75-75
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• 2010

3D 패키징 기술은 전기소자의 소형화, 고용량화, 저전력화, 높은 신뢰성등의 요구와 함께 그 중요성이 대두대고 있다. 이러한 3D 패키징의 연결방법은 와이어 본딩 또는 플립칩등의 기존의 방법에서 TSV(Through Silicon Via)를 이용하여 적층하는 방법이 주목받고 있다. TSV는 기존의 와이어 본딩과 비교하여 고집적도, 빠른 신호전달, 낮은 전력소비 등의 장점을 가지고 있어 많은 연구가 진행되고 있다. TSV의 세부 공정 중 비아필링(Via filling)기술은 I/O수 증가와 미세피치화에 따른 비아(Via) 직경의 감소 및 종횡비(Via Aspect Ratio)증가로 인해 기존 필링 공정으로는 한계가 있다. 기존의 비아 홀(Via hole)에 금속을 필링하기 위한 방법으로 전기도금법이 많이 사용되고 있으나, 전기도금법은 전기도금액 조성, 첨가제의 종류, 전류밀도, 전류모드 등에 따라 결과물에 큰 차이가 발생되어, 최적공정조건의 도출이 어렵다. 또한 20um이하의 비아직경과 높은 종횡비로 인하여 충진시 void형성등의 문제점이 발생하기도 한다. 본 연구에서는 용융솔더와 진공을 이용하여 비아를 필링시켰다. 이 방법은 관통된 비아가 형성된 웨이퍼 양단에 압력차를 주어, 작은 직경을 갖는 비아 홀의 표면장력을 극복하고, 용융상태의 솔더가 관통된 비아 홀 내부로 필링되는 방법이다. 관통 비아홀이 형성 된 웨이퍼 위에 솔더페이스트를 $250^{\circ}C$이상 온도를 가해 용융상태로 만든 후 웨이퍼 하부에 진공을 형성하여 필링하는 방법과 용융솔더를 노즐을 통하여 위쪽으로 유동시켜 그 위에 비아홀이 형성된 웨이퍼를 접촉하고 웨이퍼 상부에 진공을 형성하여 필링하는 방법으로 실험을 각각 실시하였다. 이 때, 웨이퍼 두께는 100um이하이며 홀 직경은 20, 30um, 웨이퍼 상부와 하부의 진공차는 약 0.02~0.08Mpa, 진공 유지시간은 1~3s로 실시하여 최적 조건을 고찰하였다. 각 조건에 따른 필링 후 단면을 전자현미경(FE-SEM)을 통해 관찰하였다. 실험 결과 0.04Mpa 이상에서 1s내의 시간에 모든 비아홀이 기공(Void)없이 완벽하게 필링되는 것을 관찰하였으며 이 결과는 기존의 방법에 비하여 공정시간을 감소시켜 생산성이 대폭 향상 될 수 있는 방법임을 확인하였다.

• Proceedings of the KWS Conference
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• 2007.11a
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• pp.229-231
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• 2007

Recently, 3D-electronic packaging by TSV is in interest. TSV(Through Silicon Via) is a interconnection hole on Si-wafer filled with conducting metal such as Copper. In this research, chips with TSV are connected by electroplated Sn bump without PR. Then chips with TSV are put together and stacked by the methode of Reflow soldering. The stacking was successfully done and had no noticeable defects. By eliminating PR process, entire process can be reduced and makes it easier to apply on commercial production.

• Journal of Information Display
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• v.2 no.3
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• pp.60-65
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• 2001

Lateral type poly-silicon field emitters were fabricated by utilizing the LOCOS (Local Oxidation of Silicon) process. For the implementation 'of an ideal field emission device with quasi-zero tunneling barrier, a new and fundamental approach has used conducted by introducing an intelligent carbon-based thin layer on the cathode tip surface via a field-assisted self-aligning of carbon (FASAC) process. Fundamental lowering of the turn-on field for the electron emission was feasible through the control of both the tip shape and surface barrier height.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.196-203
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• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.23-29
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• 2010

This paper presents a method for constructing a memory system using defective memory chips comprising faulty storage blocks. The three-dimensional memory system introduced here employs a die-stacked structure of faulty memory chips. Signals lines passing through the through-silicon-vias (TSVs) connect chips in the defect tolerant structure. Defective chips are classified into several groups each group comprising defective chips having faulty blocks at the same location. A defect tolerant memory system is constructed using chips from different groups. Defect-free storage blocks from spare chips replace faulty blocks using additional routing circuitry. The number of spare chips for defect tolerance is $s={\ulcorner}(k{\times}n)/(m-k){\urcorner}$ to make a system defect tolerant for (n+s) chips with k faulty blocks among m independently addressable blocks.

• The Korean Journal of Ceramics
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• v.7 no.1
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• pp.36-40
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• 2001

In order to fabricate uncooled IR sensors for pyroelectric applications, multilayered thin films of Pt/PbTiO$_3$/Pt/Ti/Si$_3$N$_4$/SiO$_2$/Si and thermally isolating membrane structures of square-shaped/cantilevers-shaped microstructures were prepared. Cavity was also fabricated via direct silicon wafer bonding and etching technique. Metallic Pt layer was deposited by ion beam sputtering while PbTiO$_3$ thin films were prepared by sol-gel technique. Micromachining technology was used to fabricate microstructured-membrane detectors. In order to avoid a difficulty of etching active layers, silicon-nitride membrane structure was fabricated through the direct bonding and etching of the silicon wafer. Although multilayered thin film deposition and device fabrications were processed independently, these could b integrated to make IR micro-sensor devices.

• Journal of Sensor Science and Technology
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• v.14 no.6
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• pp.423-429
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• 2005

In this paper, we proposed the fabrication process of the stable e-beam evaporation and the patterning of metals layer on the polydimethylsiloxane (PDMS) substrate. The metal layer was deposited under the various deposition rate, and its effect to the electrical and mechanical properties (e.g.: adhesion-strength of metal layer) was investigated. The influence of surface roughness to the adhesion-strength was also examined via the tape test. Here, we varied the roughness by changing the reactive ion etching (RIE) duration. The electrode patterning was performed through the conventional photolithography and chemical etching process after e-beam deposition of $200{\AA}$ Ti and $1000{\AA}$ Au. As a result, the adhesion strength of metal layer on the PDMS surface was greatly improved by the oxygen plasma treatment. The e-beam evaporation on the PDMS surface is known to create the wavy topography. Here, we found that such wavy patterns do not effect to the electrical and mechanical properties. In conclusion, the metal patterns with minimum $20{\mu}m$ line width was produced well via the our fabrication process, and its electrical conductance was almost similar to the that of metal patterns on the silicon or glass substrates.

• Korean Journal of Materials Research
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• v.22 no.7
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• pp.374-378
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• 2012

In an effort to overcome the problems which arise when fabricating high-aspect-ratio TSV(through silicon via), we performed experiments involving the void-free Cu filling of a TSV(10~20 ${\mu}m$ in diameter with an aspect ratio of 5~7) by controlling the plating DC current density and the additive SPS concentration. Initially, the copper deposit growth mode in and around the trench and the TSV was estimated by the change in the plating DC current density. According to the variation of the plating current density, the deposition rate during Cu electroplating differed at the top and the bottom of the trench. Specifically, at a current density 2.5 mA/$cm^2$, the deposition rate in the corner of the trench was lower than that at the top and on the bottom sides. From this result, we confirmed that a plating current density 2.5 mA/$cm^2$ is very useful for void-free Cu filling of a TSV. In order to reduce the plating time, we attempted TSV Cu filling by controlling the accelerator SPS concentration at a plating current density of 2.5 mA/$cm^2$. A TSV with a diameter 10 ${\mu}m$ and an aspect ratio of 7 was filled completely with Cu plating material in 90 min at a current density 2.5 mA/$cm^2$ with an addition of SPS at 50 mg/L. Finally, we found that TSV can be filled rapidly with plated Cu without voids by controlling the SPS concentration at the optimized plating current density.