• 제목/요약/키워드: Three Level Converter

검색결과 222건 처리시간 0.022초

1차측 클램핑 다이오드를 이용한 ZVS Three-Level DC/DC 컨버터에 관한 연구 (A Study on the Zero-Voltage-Switching Three-Level DC/DC Converter using Primary Clamping Diodes)

  • 김용
    • 조명전기설비학회논문지
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    • 제27권12호
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    • pp.101-108
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    • 2013
  • This paper presents A Zero-Voltage-Switching(ZVS) Three-Level DC/DC Converter using Primary Clamping Diodes. The Previous ZVS Three-Level DC/DC converter realizes ZVS for the switches with the use of the leakage inductance(or external resonant inductance) and the output capacitors of the switches, however the rectifier diodes suffer from recovery which results in oscillation and voltage spike. In order to solve this problem, this paper proposes a novel ZVS Three-Level DC/DC converter, which introduces two clamping diodes to the basic Three-Level converter to eliminate the oscillation and clamp the rectified voltage to the reflected input voltage.

Analysis of a New Parallel Three-Level Zero-Voltage Switching DC Converter

  • Lin, Bor-Ren;Chen, Jeng-Yu
    • Journal of Electrical Engineering and Technology
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    • 제10권1호
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    • pp.128-137
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    • 2015
  • A novel parallel three-level zero voltage switching (ZVS) DC converter is presented for medium voltage applications. The proposed converter includes three sub-circuits connected in parallel with the same power switches to share load current and reduce the current stress of passive components at the output side. Thus, the size of the output chokes is reduced and the switch counts in the proposed converter are less that in the conventional parallel three-level DC/DC converter. Each sub-circuit combines one half-bridge converter and one three-level converter. The transformer secondary windings of these two converters are connected in series in order to reduce the size of output inductor. Due to the three-level circuit topology, the voltage stress of power switches is equal to $V_{in}/2$. Based on the resonant behavior by the output capacitance of power switches and the leakage inductance (or external inductance) at the transition interval, each switch can be turned on under ZVS. Finally, experiments based on a 2 kW prototype are provided to verify the performance of the proposed converter.

출력 전압 밸런싱 기능을 가진 비절연형 3-레벨 고승압 부스트 컨버터 (A Non-Isolated 3-Level High Step-Up Boost Converter With Output Voltage Balancing)

  • 윤성현;강혜민;차헌녕;김흥근
    • 전력전자학회논문지
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    • 제20권5호
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    • pp.464-470
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    • 2015
  • In this paper, a non-isolated three-level high step-up boost converter with output voltage balancing is proposed. By adding one extra inductor to the conventional three-level boost converter, the proposed converter is derived. Compared with the traditional boost converter and the three-level boost converter, the proposed converter can obtain very high voltage conversion ratio, and the voltage and current stress of switching devices and diodes are reduced. A 2.7 kW prototype converter is built and tested to verify performances of the proposed converter.

A Study on the Secondary Rectification-Methods for the Three-Level Converter

  • Bae, Jin-Yong;Kim, Yong
    • Journal of Electrical Engineering and Technology
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    • 제2권1호
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    • pp.81-88
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    • 2007
  • This paper proposes a coupled inductor-based rectifier of a Three-Level (TL) DC/DC converter and compares the rectification methods of a TL converter. The CICDR- TL (Coupled Inductor Current Doubler Rectifier Three-Level) converter achieves ZVS (Zero Voltage Switching) for the switches in a wide load range. CDR (Current Doubler Rectifier) and CICDR Three-Level converter have low voltage and current ripple. Advantages and disadvantages of topology compared to the rectifier of bridge, center-tap, CDR, and CICDR are discussed. Experimental estimation results are obtained on a 27V, 60A DC/DC TL converter prototype for the 1.8kW, 40kHz IGBT based experimental circuit.

결합 인덕터를 이용한 3-레벨 Zeta 컨버터 (Three-Level Zeta Converter using a Coupled Inductor)

  • 이승재;양민권;허준;최우영
    • 전력전자학회논문지
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    • 제21권3호
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    • pp.191-199
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    • 2016
  • Conventional two-level Zeta converters have drawbacks, such as high voltage stresses and high current ripples. To address these problems, a three-level Zeta converter that uses a couple inductor is proposed in this study. The proposed converter utilizes the three-level power switching circuit to reduce the voltage stresses and inductor current ripples. Compared with the conventional converter, the proposed converter can improve power efficiency and power density. A 500 W prototype circuit is used to verify the operation and performance of the proposed converter via experimental results.

인터리빙 동작을 위한 하단 인덕터를 갖는 3-Level Boost Converter (3-Level Boost Converter Having Lower Inductor for Interleaving Operation)

  • 이강문;백승우;김학원;조관열;강정원
    • 전력전자학회논문지
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    • 제26권2호
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    • pp.96-105
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    • 2021
  • Large-scale power converters consist of series or parallel module combinations. In these modular converter systems, the interleaving technique can be applied to improve capacitor reliability by reducing the ripple of the I/O current in which each module operates as a phase difference. However, when applying the interleaving technique for conventional three-level boost converters, the short-circuit period of the converter can be an obstacle. Such problem is caused by the absence of a low-level inductor of the conventional three-level boost converter. To solve this problem, a three-level boost converter with a low-level inductor is proposed and analyzed to enable interleaved operation. In the proposed circuit, the current ripple of the output capacitor depends on the neutral point connections between the modules. In this study, the ripple current is analyzed by the neutral point connections of the three-level boost converter that has a low-level inductor, and the effectiveness of the proposed circuit is proven by simulation and experiment.

A Parallel Hybrid Soft Switching Converter with Low Circulating Current Losses and a Low Current Ripple

  • Lin, Bor-Ren;Chen, Jia-Sheng
    • Journal of Power Electronics
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    • 제15권6호
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    • pp.1429-1437
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    • 2015
  • A new parallel hybrid soft switching converter with low circulating current losses during the freewheeling state and a low output current ripple is presented in this paper. Two circuit modules are connected in parallel using the interleaved pulse-width modulation scheme to provide more power to the output load and to reduce the output current ripple. Each circuit module includes a three-level converter and a half-bridge converter sharing the same lagging-leg switches. A resonant capacitor is adopted on the primary side of the three-level converter to reduce the circulating current to zero in the freewheeling state. Thus, the high circulating current loss in conventional three-level converters is alleviated. A half-bridge converter is adopted to extend the ZVS range. Therefore, the lagging-leg switches can be turned on under zero voltage switching from light load to full load conditions. The secondary windings of the two converters are connected in series so that the rectified voltage is positive instead of zero during the freewheeling interval. Hence, the output inductance of the three-level converter can be reduced. The circuit configuration, operation principles and circuit characteristics are presented in detail. Experiments based on a 1920W prototype are provided to verify the effectiveness of the proposed converter.

1차측 환류 다이오드를 제거한 ZVS Three-Level DC/DC 컨버터에 관한 연구 (A Study on the Zero-Voltage-Switching Three-Level DC/DC Converter without Primary Freewheeling Diodes)

  • 전용진;김용;배진용;이은영;최근수
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2005년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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    • pp.183-187
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    • 2005
  • A Zero-Voltage-Switching(ZVS) Three-Level Converter realizes ZVS for the switches with the use of the leakage inductance(or external resonant inductance) and the output capacitors of the switches, however; the rectifier diodes suffer from recovery which results in oscillation and voltage spike. In order to solve this problem, this paper proposes a novel ZVS Three-Level converter, which introduces two clamping diodes to the basic Three-Level converter to eliminate the oscillation and clamp the rectified voltage to the reflected input voltage, the proposed ZVS Three-Level converter can be simplified by removing the two freewheeling diodes.

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단상 Three-level boost converter의 역률개선 (Power Factor Improvement of Single-Phase Three-level Boost Converter)

  • 서영조
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2000년도 전력전자학술대회 논문집
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    • pp.384-387
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    • 2000
  • In this paper Power factor correction circuit of single-phase three-level boost converter is proposed. The advantage of the proposed control scheme for three-level boost converter are low blocking voltage of each power device low THD(Total Harmonic Distortion) and high power factor. The control scheme is based on the current comparator capacitor compensator and region detector, In simulations the proposed system is validated.

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SVPWM Strategies for Three-level T-type Neutral-point-clamped Indirect Matrix Converter

  • Tuyen, Nguyen Dinh;Phuong, Le Minh;Lee, Hong-Hee
    • Journal of Power Electronics
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    • 제19권4호
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    • pp.944-955
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    • 2019
  • In this paper, the three-level T-type neutral-point-clamped indirect matrix converter topology and the relative space vector modulation methods are introduced to improve the voltage transfer ratio and output voltage performance. The presented converter topology is based on combinations of cascaded-rectifier and three-level T-type neutral-point-clamp inverter. It can overcome the limitation of voltage transfer ratio of the conventional matrix converter and the high voltage rating of power switches of conventional matrix converter. Two SVPWM strategies for proposed converter are described in this paper to achieve the advantages features such as: sinusoidal input/output currents and three-level output voltage waveforms. Results from Psim 9.0 software simulation are provided to confirm the theoretical analysis. Hence, a laboratory prototype was implemented, and the experimental results are shown to validate the simulation results and to verify the effectiveness of the proposed topology and modulation strategies.