• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.188-188
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• 2011

Recently, scaling down of ULSI (Ultra Large Scale Integration) circuit of CMOS (Complementary Meta Oxide Semiconductor) based electronic devices, the electronic devices, become much faster and smaller size that are promising property of semiconductor market. However, very narrow interconnect line width has some disadvantages. Deposition of conformal and thin barrier is not easy. And metallization process needs deposition of diffusion barrier and glue layer for EP/ELP deposition. Thus, there is not enough space for copper filling process. In order to get over these negative effects, simple process of copper metallization is important. In this study, Cu-V alloy layer was deposited using of DC/RF magnetron sputter deposition system. Cu-V alloy film was deposited on the plane SiO2/Si bi-layer substrate with smooth surface. Cu-V film's thickness was about 50 nm. Cu-V alloy film deposited at $150^{\circ}C$. XRD, AFM, Hall measurement system, and AES were used to analyze this work. For the barrier formation, annealing temperature was 300, 400, $500^{\circ}C$ (1 hour). Barrier thermal stability was tested by I-V(leakage current) and XRD analysis after 300, 500, $700^{\circ}C$ (12 hour) annealing. With this research, over $500^{\circ}C$ annealed barrier has large leakage current. However vanadium-based diffusion barrier annealed at $400^{\circ}C$ has good thermal stability. Therefore thermal stability of vanadium-based diffusion barrier is desirable for copper interconnection.

• 전자공학회논문지D
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• 제36D권6호
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• pp.35-43
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• 1999

본 논문에서는 자유 공간 광 연결 구도에 적합한 새로운 구조의 광 thyristor를 제안하고, 이 소자의 성능을 기존의 광 thyristor와 비교 평가하였다. 제안된 광 thyristor는 얇은 가운데 층들을 갖는 완전 공핍 광 thyristor로서 빠른 스위칭 속도와 향상된 광 반응성을 위하여 다중 양자 우물(multiple quantum wells)과 하부 거울층(bottom mirror)을 이용하였다. 기존 광 thyristor와의 성능 비교를 위한 모의실험은 전류 중심(current oriented) 연결 접합 모델(coupled junction model)과 박막층의 특성 행렬(thin film characteristic matrix), 그리고 van Roosbroeck-Shockley relation을 이용하였다. 모의 실험을 통하여 소자의 구성 물질, 두께, 불순물 농도등의 물리적 인자들이 같은 경우, 기존의 광 thyristor에 비하여 제안된 광 thyristor의 스위칭 에너지가 0.43 배 줄고, 발광 효율은 1.76 배 증가하며, 연동 동작(cascadable operation)시 bit-rate는 1.61 배 증가함을 알 수 있었다.

• Carbon letters
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• 제21권
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• pp.68-73
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• 2017

We have demonstrated the production of thin films containing multilayer graphene-coated copper nanoparticles (MGCNs) by a commercial electrodeposition method. The MGCNs were produced by electrical wire explosion, an easily applied technique for creating hybrid metal nanoparticles. The nanoparticles had average diameters of 10-120 nm and quasi-spherical morphologies. We made a complex-electrodeposited copper thin film (CETF) with a thickness of $4.8{\mu}m$ by adding 300 ppm MGCNs to the electrolyte solution and performing electrodeposition. We measured the electric properties and performed corrosion testing of the CETF. Raman spectroscopy was used to measure the bonding characteristics and estimate the number of layers in the graphene films. The resistivity of the bare-electrodeposited copper thin film (BETF) was $2.092{\times}10^{-6}{\Omega}{\cdot}cm$, and the resistivity of the CETF after the addition of 300 ppm MGCNs was decreased by 2% to ${\sim}2.049{\times}10^{-6}{\Omega}{\cdot}cm$. The corrosion resistance of the BETF was $9.306{\Omega}$, while that of the CETF was increased to 20.04 Ω. Therefore, the CETF with MGCNs can be used in interconnection circuits for printed circuit boards or semiconductor devices on the basis of its low resistivity and high corrosion resistance.

• 마이크로전자및패키징학회지
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• 제9권3호
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• pp.1-6
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• 2002

A low temperature process technology of copper thin films has been developed by a chemical vapor deposition technology for multi-level metallzations in ULSI fabrication. The copper films were deposited on TiN/Si substrates in helium atmosphere with the substrate temperature between $130^{\circ}C$ and $250^{\circ}C$. In order to get more reliable metallizations, effects on the post-annealing treatment to the electrical properties of the copper films have been investigated. The Cu films were annealed at the $5 \times10^{-6}$ Torr vacuum condition and the electrical resistivity and the nano-structures were measured for the Cu films. The electrical resistivity of Cu films shown to be reduced by the post-annealing. The electrical resistivity of 2.0 $\mu \Omega \cdot \textrm{cm}$ was obtained for the sample deposited at the substrate temperature of $180^{\circ}C$ after vacuum annealed at $300^{\circ}C$. The resistivity variations of the films was not exactly matched with the size of the nano-structures of the copper grains, but more depended on the contamination of the copper films.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2008년도 추계학술대회A
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• pp.1553-1555
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• 2008

Super-hydrophobic treated Polyimide film was used as a flexible substrate for developing a new method of metallization. Hydrophilic patterns were fabricated by IN irradiation through shadow mask. Patterned super-hydrophobic substrate was dipped into a bath containing silver nano ink Silver ink was only coated on hydrophilic patterned area. Metal lines of $600{\mu}m$ pitch were fabricated successfully. However, their thickness was too thin to serve as interconnection. To overcome this problem, iterative dipping was conducted. After repeating five times, the thickness of silver metal lines were increased to over than $2{\mu}$. After heat treatment of silver lines, their resistivities were reduced to order of $30{\mu}{\Omega}$-cm the similar level of values reported in other literatures. So, a new method of metallization has high potential for application of RFID antenna and flexible electronics substrates.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1996년도 추계학술대회 논문집
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• pp.172-176
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• 1996

The rapid structural change of ULSI chip includes minimum features, multilevel interconnection and large diameter wafers. Demands for the advanced chip structure necessitates the development of enhanced deposition, etching and planarization techniques. Planarization refers to a process that make rugged surfaces flat and uniform. One of the emerging technologies for planarization is chemical mechanical polishing(CMP). Chemical and mechanical removal actions occur during CMP, and both appear to be closely interrelated. The purpose of this study is the optimal application of the slurry to the various types of device materials during CMP. We investigates the effect of slurry on CMP characteristics for thermal oxide and sputtered Al blanket wafers. Results from the polishing rate and the uniformity of residual film include mechanical and chemical reactions between several set of slurry and work material.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2003년도 춘계학술발표회 초록집
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• pp.41-41
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• 2003

텅스텐(W)은 높은 thermal stability 와 process compatibility 및 우수한 corrosion r resistance 둥으로 integrated circuit (IC)의 gate 및 interconnection 둥으로의 활용이 대두되고 있으며, 차세대 thin film transistor liquid crystal display (TFT-LCD)의 gate 및 interconnection m materials 둥으로 사용되고 았다. 그러나, 이러한 장점을 가지고 있는 팅스텐 박막이 실제 공정상에 적용되가 위해서는 건식 식각이 주로 사용되는데, 이는 wet chemical 을 이용한 습식 식각을 사용할 경우 낮은 etch rate, line width 의 감소 및 postetch residue 잔류 동의 문제가 발생하기 때문이다. 또한 W interconnection etching 을 하기 위해서는 높은 텅스텐 박막의 etch rate 과 하부 layer ( (amorphous silicon 또는 poly-SD와의 높은 etch selectivity 가 필수적 이 라 할 수 있다. 그러 나, 지금까지 연구되어온 결과에 따르면 텅스탠과 하부 layer 와의 etch selectivity 는 2 이하로 매우 낮게 관찰되고 았으며, 텅스텐의 etch rate 또한 150nm/min 이하로 낮은 값을 나타내고 있다. 따라서 본 연구에서는 halogen-based inductively coupled plasma 를 이용하여 텅스텐 박막 식각시 여러 가지 첨가 가스에 따른 높은 텅스탠 박막의 etch rate 과 하부 layer 와의 높은 etch s selectivity 를 얻고자 하였으며, 그에 따른 식각 메커니즘에 대하여 알아보고자 하였다. $CF_4/Cl_2$ gas chemistry 에 첨 가 가스로 $N_2$와 Ar을 첨 가할 경 우 텅 스텐 박막과 하부 layer 간의 etch selectivity 증가는 관찰되지 않았으며, 반면에 첨가 가스로 $O_2$를 사용할 경우, $O_2$의 첨가량이 증가함에 따라 etch s selectivity 는 계속적으로 증가렴을 관찰할 수 있었다. 이는 $O_2$ 첨가에 따라 형성되는 WOF4 에 의한 텅스텐의 etch rates 의 감소에 비하여, $Si0_2$ 등의 형성에 의한 poly-Si etch rates 이 더욱 크게 감소하였기 때문으로 사료된다. W 과 poly-Si 의 식각 특성을 이해하기 위하여 X -ray photoelectron spectroscopy (XPS)를 사용하였으며, 식각 전후의 etch depth 를 측정하기 위하여 stylus p pmfilometeT 를 이용하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.294-294
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• 2010

Over the last decade, dye-sensitized solar cell (DSSC) has attracted much attention due to the high solar-to-electricity conversion efficiency up to 10% as well as low cost compared with p-n junction photovoltaic devices. DSSC is composed of mesoporous TiO2 nanoparticle electrodes coated with photo-sensitized dye, the redox electrolyte and the metal counter electrode. The performances of DSSC are dependent on constituent materials and interface as well as device structure. Replacing the heavy glass substrate with plastic materials is crucial to enlarge DSSC applications for the competition with inorganic based thin film photovoltaic devices. One of the biggest problems with plastic substrates is their low-temperature tolerance, which makes sintering of the photoelectrode films impossible. Therefore, the most important step toward the low-temperature DSSC fabrication is how to enhance interparticle connection at the temperature lower than $150^{\circ}C$. In this talk, the key issues for high efficiency plastic solar cells will be discussed, and several strategies for the improvement of interconnection of nanoparticles and bendability will also be proposed.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2000년도 제1회 학술대회 논문집
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• pp.71-72
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• 2000

The design of large area thin film transistor liquid crystal displays (TFT-LCDs) requires consideration of cross-talks between the data lines and pixel electrodes. These limits are imposed by the mutual coupling capacitances present in a pixel. The mutual coupling capacitance causes a pixel voltage error. In this study, semi-empirical model, which is adopted from VLSI interconnection capacitance calculations, is used to calculate mutual coupling capacitances. With calculated mutual coupling capacitances and arbitrary given image pattern, the root mean square (RMS) voltage of pixel is calculated to see vertical cross-talk from the first to the last column. The information obtained this study can be utilized to design the larger area and finer image quality panel.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 추계학술대회 논문집
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• pp.557-560
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• 1999

The design of large area thin film transistor liquid crystal displays (TFT-LCDs) requires consideration of cross-talks between the data lines and pixel electrodes. These limits are imposed by the parasitic capacitive elements present in a pixel. The capacitive coupling of the data line signal onto the pixel causes a pixel voltage error. In this study semi-empirical capacitance model which is adopted from VLSI interconnection capacitance calculations was used to calculate mutual coupling capacitances. With calculated mutual coupling capacitances and given image pattern, the root mean square(RMS) voltage of pixel is calculated to see vertical cross-talk from the first to the last column. The information obtained from this study could be utilized to design the larger area and finer image quality panel.