• Korean Journal of Materials Research
• /
• v.33 no.11
• /
• pp.475-481
• /
• 2023

Recently, the electron transport layer (ETL) has become one of the key components for high-performance perovskite solar cell (PSC). This study is motivated by the nonreproducible performance of ETL made of spin coated SnO₂ applied to a PSC. We made a comparative study between tin oxide deposited by atomic layer deposition (ALD) or spin coating to be used as an ETL in N-I-P PSC. 15 nm-thick Tin oxide thin films were deposited by ALD using tetrakisdimethylanmiotin (TDMASn) and using reactant ozone at 120 ℃. PSC using ALD SnO₂ as ETL showed a maximum efficiency of 18.97 %, and PSC using spin coated SnO₂ showed a maximum efficiency of 18.46 %. This is because the short circuit current (Jsc) of PSC using the ALD SnO₂ layer was 0.75 mA/cm² higher than that of the spin coated SnO₂. This result can be attributed to the fact that the electron transfer distance from the perovskite is constant due to the thickness uniformity of ALD SnO₂. Therefore ALD SnO₂ is a candidate as a ETL for use in PSC vacuum deposition.

• 한국신재생에너지학회:학술대회논문집
• /
• 2010.06a
• /
• pp.59.1-59.1
• /
• 2010

Aluminum-induced crystallization (AIC) of amorphous silicon (a-Si) is studied with the structure of a glass/Al/$SiO_2$/a-Si, in which the $SiO_2$ layer has micron-sized laser holes in the stack. An oxide layer between aluminum and a-Si thin films plays a significant role in the metal-induced crystallization (MIC) process determining the properties such as grain size and preferential orientation. In our case, the crystallization of a-Si is carried out only through the key hole because the $SiO_2$ layer is substantially thick enough to prevent a-Si from contacting aluminum. The crystal growth is successfully realized toward the only vertical direction, resulting a crystalline silicon grain with a size of $3{\sim}4{\mu}m$ under the hole. Lateral growth seems to be not occurred. For the AIC experiment, the glass/Al/$SiO_2$/a-Si stacks were prepared where an Al layer was deposited on glass substrate by DC sputter, $SiO_2$ and a-Si films by PECVD method, respectively. Prior to the a-Si deposition, a $30{\times}30$ micron-sized hole array with a diameter of $1{\sim}2{\mu}m$ was fabricated utilizing the femtosecond laser pulses to induce the AIC process through the key holes and the prepared workpieces were annealed in a thermal chamber for 2 hours. After heat treatment, the surface morphology, grain size, and crystal orientation of the polycrystalline silicon (pc-Si) film were evaluated by scanning electron microscope, transmission electron microscope, and energy dispersive spectrometer. In conclusion, we observed that the vertical crystal growth was occurred in the case of the crystallization of a-Si with aluminum by the MIC process in a small area. The pc-Si grain grew under the key hole up to a size of $3{\sim}4{\mu}m$ with the workpiece.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.36D no.10
• /
• pp.9-16
• /
• 1999

When the conventional IPD (inter-poly-dielctrics) layer with ONO(oxide-nitride-oxide) structure was used in the Flash EEPROM cell, its data retention characteristics were significanfly degraded because the top oxide of the ONO layer was etched off due to the cleaning process used in the gate oxidation process for the peripheral MOSFETs. When the IPD layer with the ONON(oxide-nitride-oxide-nitride) was used there, however, its data retention characteristics were much improved because the top nitride of the ONON layer protected the top oxide from being etched in the cleaning process. For the modelling of the data retention characteristics of the Flash EEPROM cell with the ONON IPD layer, the decrease of the threshold voltage cue to the charge loss during the bake was here given by the empirical relation ${\Delta}V_t\; = \;{\beta}t^me^{-ea/kT}$ and the values of the ${\beta}$=184.7, m=0.224, Ea=0.31 eV were obtained with the experimental measurements. The activation energy of 0.31eV implies that the decrease of the threshold voltage by the back was dur to the movement of the trapped electrons inside the inter-oxide nitride layer. On the other hand, the results of the computer simulation using the model were found to be well consistent with the results of the electrical measurements when the thermal budget of the bake was not high. However, the latter was larger then the former in the case of the high thermal budger, This seems to be due to the leakage current generated by the extraction of the electrons with the bake which were injected into the inter-oxide niride later and were trapped there during the programming, and played the role to prevent the leakage current. To prevent the generation of the leakage current, it is required that the inter-oxide nitride layer and the top oxide layer be made as thin and as thick as possible, respectively.

• Journal of the Microelectronics and Packaging Society
• /
• v.14 no.2 s.43
• /
• pp.17-21
• /
• 2007

Dense and periodic arrays of holes and Si nano dots were fabricated on silicon substrate. The nanopatterned holes were approximately $15{\sim}40nm$ wide, 40 nm deep and $40{\sim}80\;nm$ apart. To obtain nano-size patterns, self?assembling diblock copolymer were used to produce layer of hexagonaly ordered parallel cylinders of polymethylmethacrylate (PMMA) in polystyrene(PS) matrix. The PMMA cylinders were degraded and removed with acetic acid rinse to produce a PS. $100\;{\AA}-thick$ Au thin film was deposited by using e-beam evaporator. PS template was removed by lift-off process. Arrays of Au nano dots were transferred by using Fluorine-based reactive ion etching(RE). Au nano dots were removed by sulfuric acid. Si nano dots size and height were $30{\sim}70\;nm$ and $10{\sim}20\;nm$ respectively.

• Korean Journal of Optics and Photonics
• /
• v.10 no.3
• /
• pp.181-187
• /
• 1999

We prepared the side-chain type nonlinear optical NPP(N-(6-nitrophenyl)-(L)-prolinol) polymer films by spin coating method. Ellipsometric spectra were in situ collected by using spectroscopic phase modulated ellipsometer while the NPP polymer films were being corona poled at the temperature above glass transition. We calculated film thickness and the refractive index dispersion by modeling the spectro-ellipsometry data in transparent region. We also calculated the refractive index and the extinction coefficient of the polymer films by numerically inverting the spectro-ellipsometry data in absorbing region, while the previously determined film thickness was used. The independently determined extinction coefficient spectra from the analysis of transmission spectra were compared with those by spectro-ellipsometry and they showed an excellent agreement with each other. From the analysis of the complex refractive index change of the NPP polymer thin films induced by the corona poling, we could determine the vertical complex refractive index and the horizontal complex refractive index separately. Using the volume fraction of the vertical component f⊥, the degree of poling of poled NPP polymer films was quantitatively addressed. It is suggested that the present method can be used to quantitatively address the degree of poling in an absolute manner and to depth profile the poled fraction of thick polymer films. It will be useful to understand the structural change of polymer films and hence the poling mechanism during the poling process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.35 no.1
• /
• pp.44-49
• /
• 2022

In this paper, we investigated current (I)- and voltage (V)-sweeping properties in a double-stack structure, Ge₂Sb₂Te₅/Ti/W-doped Ge₈Sb₂Te₁₁, a candidate medium for applications to multilevel phase-change memory. 200-nm-thick and W-doped Ge₂Sb₂Te₅ and W-doped Ge₈Sb₂Te₁₁ films were deposited on p-type Si(100) substrate using magnetron sputtering system, and the sheet resistance was measured using 4 point-probe method. The sheet resistance of amorphous-phase W-doped Ge₈Sb₂Te₁₁ film was about 1 order larger than that of Ge₂Sb₂Te₅ film. The I- and V-sweeping properties were measured using sourcemeter, pulse generator, and digital multimeter. The speed of amorphous-to-multilevel crystallization was evaluated from a graph of resistance vs. pulse duration (t) at a fixed applied voltage (12 V). All the double-stack cells exhibited a two-step phase change process with the multilevel memory states of high-middle-low resistance (HR-MR-LR). In particular, the stable MR state is required to guarantee the reliability of the multilevel phase-change memory. For the Ge₂Sb₂Te₅ (150 nm)/Ti (20 nm)/W-Ge₈Sb₂Te₁₁ (50 nm), the phase transformations of HR→MR and MR→LR were observed at t<30ns and t<65ns, respectively. We believe that a high speed and stable multilevel phase-change memory can be optimized by the double-stack structure of proper Ge-Sb-Te films separated by a barrier metal (Ti).

• Journal of the Korean Ceramic Society
• /
• v.39 no.2
• /
• pp.120-125
• /
• 2002

AC powder EL devices were fabricated by screen printing method with the dielectric materials in insulating layer and the electrical resistivity of rear electrode. Brightness and current density were measured at voltage range of 50∼300 $V_{rms}$ to estimate optoelectrical properties of AC powder EL devices, respectively. Frequency generator was used as system producing frequency and voltage of a sine wave. Brightness and current density were measured by luminometer and multimeter. Also, dielectric constant for dielectric layer was measured by impedance analyser after preparing thick film. Dielectric constant was improved with amount of $TiO_2$ to $BaTiO_3$ powder. By applying such a process to dielectric layer of low cost AC powder EL device, brightness was improved to 50 cd/$m^2$ at similar current density. Dielectric constant $BaTiO_3$ powder by solution combustion process is better than commercial $BaTiO_3$ powder. By applying to that of low power consumption AC powder EL device, brightness was improved to 85 cd/$m^2$. Brightness of AC powder EL device was relatively decreased by control of electrical resistivity of rear electrode, current density was also decreased.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2011.02a
• /
• pp.134-134
• /
• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.17 no.1
• /
• pp.7-15
• /
• 2004

The ferroelectric SBT thin films as a material of capacitors for non-volatile FRAMs have some problems that its remanent polarization value is relatively low and the crystallization temperature is quite high abovc 80$0^{\circ}C$. Therefore, in this paper, SBTN solution with S $r_{0.9}$B $i_{2.1}$T $a_{1.8}$N $b_{0.2}$$O_{9}$ composition was synthesized by sol-gel method. Sr(O $C_2$ $H_{5}$)$_2$, Bi(TMHD)$_3$, Ta(O $C_2$ $H_{5}$)$_{5}$and Nb(O $C_2$ $H_{5}$)$_{5}$ were used as precursors, which were dissolved in 2-methoxyethanol. SBTN thin films with 200 nm thickness were deposited on Pt/Ti $O_2$/ $SiO_2$/Si substrates by spin-coating. UV-irradiation in a power of 200 W for 10 min and rapid thermal annealing in a 5-Torr-oxygen ambient at 76$0^{\circ}C$ for 60 sec were used to promote crystallization. The films were well crystallized and fine-grained after annealing at $650^{\circ}C$ in oxygen ambient. The electrical characteristics of 2Pr=11.94 $\mu$C/$\textrm{cm}^2$, Ps＋/Pr＋=0.54 at the applied voltage of 5 V were obtained for a 200-nm-thick SBTN films. This results show that 2Pr values of the UV irradiated and rapid thermal annealed SBTN thin films at the applied voltage of 5 V were about 57% higher than those of no additional processed SBTN thin films. thin films.lms.s.s.

• Membrane Journal
• /
• v.24 no.6
• /
• pp.453-462
• /
• 2014

Thin film composite (TFC) polyamide (PA) membranes were prepared on polyester (PET) nonwoven reinforced polysulfone supports for forward osmosis (FO) processes. PSF (polysulfone) supports were prepared via the phase inversion process from PSF casting solutions in dimethyl formamide (DMF) solvents (19 wt%) by using a PET nonwoven (thickness of $100{\mu}m$) as a mechanical reinforcing material for reverse osmosis (RO) membrane. The PSF support from 19 wt% of DMF/PSF casting solution showed sponge-like morphology and asymmetric internal structure. To reduce the internal concentration polarization in FO operation, thin ($20{\mu}m$ of thickness) nonwoven-supported PSF supports were prepared by using PSF/DMF casting solution (9~19 wt%). A desirable support structure with a highly porous sponge-like morphology were achieved from the thin nonwoven-supported PSF layer prepared with 9~12 wt% casting solution. A crosslinked aromatic polyamide layer was fabricated on top of each support to form a TFC PA membrane. The tested sample from 12 wt% of DMF/PSF casting solution presented outstanding FO performance, almost 5.5 times higher water flux (24.3 LMH) with low reverse salt flux (RDF, 1.5 GMH) compared to a thick nonwoven rainforced membrane (4.5 LMH of flux and 3.47 GMH of RSF). By reducing the thickness of the nonwoven and optimizing PSF concentration of casting solution, the morphology of the prepared membranes were changed from a dense structure to a porous sponge structure in the boundary area between nonwoven and PET support layer.