• 전기학회논문지
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• 제61권12호
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• pp.1944-1947
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• 2012

In this work, we investigated quench characteristics of matrix-type superconducting fault current limiters (MFCLs) according to the turn number of reactors. The reactors used in MFCLs apply magnetic field to superconducting elements within reactors when fault currents surge into MFCL systems. It makes the fast and simultaneous quenches between superconducting elements. Also reactors decrease the fault power burden of superconducting elements by bypassing the partial fault currents to itself, when quench occurs. These structure proposed in this work can be expected to achieve much more current limiting capacity even though it uses less superconductors compared with other type SFCLs. Three reactors were made by Bakelite. These reactors with the turn number of 190, 380 and 570, had the length of 270 mm and diameter of 80 mm. We reported experimental results, including fault currents, fault voltages and resistance in superconducting elements according to the turn number of reactors. We confirmed that experimental results will be useful in next future plan for the real power grid.

• International Journal of Safety
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• 제11권2호
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• pp.22-25
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• 2012

This paper deals with the problem of fault diagnosis for identifying a single fault when the number of assumed faults is larger than that of predictive variables. Principal component analysis (PCA) is employed to isolate and identify a single fault. PCA is a method to extract important information as reducing the number of large dimension in a process. The patterns of all assumed faults can be recognized by PCA and these can be employed whether a new fault is one of predefined faults or not. Through PCA, empirical models for analyzing patterns can be trained. When a single fault occurs, the pattern generated by PCA can be obtained and this is used to identify a fault. The performance of the proposed approach is illustrated in the actuator benchmark problem.

• Journal of Computing Science and Engineering
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• 제9권3호
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• pp.142-154
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• 2015

Fault localization techniques help locate faults in source codes by exploiting collected test information and have shown promising results. To precisely locate faults, the techniques require a large number of test cases that sufficiently exercise the executable statements together with the label information of each test case as a failure or a success. However, during the process of software development, developers may not have high-coverage test cases to effectively locate faults. With the test case generation techniques, a large number of test cases without expected outputs can be automatically generated. Whereas the execution results for generated test cases need to be inspected by developers, which brings much manual effort and potentially hampers fault-localization effectiveness. To address this problem, this paper presents a method to select a few test cases from a number of test cases without expected outputs for result inspection, and in the meantime selected test cases can still support effective fault localization. The experimental results show that our approach can significantly reduce the number of test cases that need to be inspected by developers and the effectiveness of fault localization techniques is close to that of whole test cases.

• 한국국방경영분석학회지
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• 제6권1호
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• pp.119-124
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• 1980

An efficient algorithm which can be employed in obtaining the minimal cut sets of a fault tree containing repeated events is introduced. A sample fault tree illustrates this algorithm. Efficiency of an algorithm is defined as the ratio of the number of minimal cut sets to the number of cut sets determined by the algorithm. An efficiency of the proposed algorithm is compared with those of two existing algorithms : Fussell and Vesely's algorithm and Bengiamin et al. 's algorithm. The proposed algorithm is shown to be more efficient than the existing two algorithms.

• 한국전기전자재료학회논문지
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• 제24권5호
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• pp.410-415
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• 2011

In this paper, we investigated the fault current limiting and the load voltage sag suppressing characteristics of the flux-lock type SFCL, designed with the additive polarity winding, according to the variations of turn number's ratio and the comparative analysis between the resistive type and the flux-lock type SFCLs were performed as well. From the analysis for the short-circuit tests, the flux-lock type SFCL designed with the larger turn number's ratio was shown to perform more effective fault current limiting and load voltage sag suppressing operations compared to the flux-lock type SFCL designed with the lower turn number's ratio through the fast quench occurrence of the high-$T_C$ superconducting (HTSC) element comprising the flux-lock type SFCL. In addition, the recovery time of the flux-lock type SFCL after the fault removed could be confirmed to be shorter in case of the flux-lock type SFCL designed with the lower turn number ratio.

• 전기학회논문지
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• 제56권1호
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• pp.66-70
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• 2007

For the design to prevent the saturation of the iron core and the effective fault current limitation, the analysis for the operation of the flux-lock type superconducting fault current limiter (SFCL) with consideration for the hysteresis characteristics of the iron core is required. In this paper, the hysteresis characteristics of the flux-lock reactor, which is an essential component of the flux-lock type SFCL, were investigated. Under normal condition, the hysteresis loss of the iron core in the flux-lock type SFCL does not happen due to its winding structure. From the equivalent circuit for the flux-lock type SFCL and the fault current limiting experiments, the hysteresis curves could be drawn. From the analysis for both the hysteresis curves and the fault current limiting characteristics due to the number of turns for the 1st and 2nd windings, the increase of the number of turns in the 2nd winding of the flux-lock type SFCL had a role to prevent the iron core from saturation.

• 한국안전학회지
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• 제31권4호
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• pp.35-41
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• 2016

In order to guarantee the process safety and prevent accidents, the deviations from normal operating conditions should be monitored and their root causes have to be identified as soon as possible. The statistical theories-based method among various fault diagnosis methods has been gaining popularity, due to simplicity and quickness. However, according to fault magnitudes, the scalar value generated by statistical methods can be changed and this point can lead to produce wrong information. To solve this difficulty, this work employs PCA (Principal Component Analysis) based method with qualitative information. In the case study of our previous study, the number of assumed faults is much smaller than that of process variables. In the case study of this study, the number of predefined faults is 19, while that of process variables is 6. It means that a fault diagnosis becomes more difficult and it is really hard to isolate a single fault with a small number of variables. The PCA model is constructed under normal operation data in order to get a loading vector and the data set of assumed faulty conditions is applied with PCA model. The significant changes on PC (Principal Components) axes are monitored with CUSUM (Cumulative Sum Control Chart) and recorded to make the information, which can be used to identify the types of fault.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제12권10호
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• pp.4774-4796
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• 2018

Wireless sensor networks are composed of a large number of inexpensive and tiny sensors used in different areas including military, industry, agriculture, space, and environment. Fault tolerance, which is considered a challenging task in these networks, is defined as the ability of the system to offer an appropriate level of functionality in the event of failures. The present study proposed an intelligent throughput descent and distributed energy-efficient mechanism in order to improve fault tolerance of the system against soft and permanent faults. This mechanism includes determining the intelligent neighborhood radius threshold, the intelligent neighborhood nodes number threshold, customizing the base paper algorithm for distributed systems, redefining the base paper scenarios for failure detection procedure to predict network behavior when running into soft and permanent faults, and some cases have been described for handling failure exception procedures. The experimental results from simulation indicate that the proposed mechanism was able to improve network throughput, fault detection accuracy, reliability, and network lifetime with respect to the base paper.

• 대한전자공학회논문지SD
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• 제40권12호
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• pp.63-71
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• 2003

IDDQ 테스팅은 CMOS VLSI 회로의 품질 및 신뢰성 향상에 중요한 테스트 방식이다. 그러나 상대적으로 느린 IDDQ 테스트를 위해서는 고려한 고장 모델에서 발생 가능한 고장의 수를 감소하거나 가능한 적은 수의 테스트 패턴을 유지하는 게 필요하다. 본 논문에서는 IDDQ 테스팅에 자주 이용되는 트랜지스터 합선 고장 모델에서 발생 가능한 고장의 수를 효과적으로 감소시킬 수 있는 효율적인 등가 고장 중첩 알고리즘을 제안한다. ISCAS 벤치마크 회로의 모의 실험을 통하여 제안된 방식의 우수한 성능을 확인하였다.

• Journal of Advanced Marine Engineering and Technology
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• 제22권5호
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• pp.687-692
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• 1998

Test pattern generation is one of most difficult problems encountered in automating the design of logic circuits. The goal is to obtain the highest fault coverage with the minimum number of test patterns for a given circuit and fault set. although there have been many deterministic algorithms and heuristics the problem is still highly complex and time-consuming. Therefore new approach-es are needed to augment the existing techniques. This paper considers the problem of test pattern improvement for combinational circuits as a restricted subproblem of the test pattern generation. The problem is to maximize the fault coverage with a fixed number of test patterns for a given cir-cuit and fault set. We propose a new approach by use of a genetic algorithm. In this approach the genetic algorithm evolves test patterns to improve their fault coverage. A fault simulation is used to compute the fault coverage of the test patterns Experimental results show that the genetic algorithm based approach can achieve higher fault coverages than traditional techniques for most combinational circuits. Another advantage of the approach is that the genetic algorithm needs no detailed knowledge of faulty circuits under test.