• 제목/요약/키워드: The Electronic Times

검색결과 3,574건 처리시간 0.034초

Room temperature growth of Mg on the Si(111)-7$\times$7 surface studied using STM and LEED

  • Lee, Dohyun;Kim, Sehun;Koo, Ja-Yong;Lee, Geunseop
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2000년도 제18회 학술발표회 논문개요집
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    • pp.150-150
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    • 2000
  • The adsorption geometry and the electronic property of Mg grown at room temperature on the Si(111)-7$\times$7 surface with various coverages have been studied by scanning tunneling microscopy (STM) and low energy electron diffraction (LEED). At low Mg coverage, the Mg atoms preferentially adsorb at the center adatom sites of the faulted half of the Si(111)-7$\times$7 surface. The adsorbed Mg atom acts as nucleophile with respect to Si atoms thus forms a stable ionic bond with the substrate Si atoms. Above 1 Ml, the 7$\times$7 surface starts to be disrupted and an amorphous Mg overlayer is formed. The LEED shows either $\delta$7$\times$7 or 1$\times$1 pattern at this coverage. When more Mg atoms were exposed, a flat and broad {{{{ { 2} over {3 } }}}}{{{{ SQRT { 3} }}}}$\times${{{{ { 2} over {3 } }}}}{{{{ SQRT { 3} }}}}R30$^{\circ}$region evolves. A flat silicide is formed at first and multi-level Mg islands having hexagonal step edges develop with increasing coverage. The scanning tunneling spectroscopy (STS) confirms the electronic properties of these Mg films on the si(111) 7$\times$7 surface at various coverages.

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PMIC용 넓은 동작전압 영역을 갖는 eFuse OTP 설계 (Design of eFuse OTP Memory with Wide Operating Voltage Range for PMICs)

  • 정우영;학문초;하판봉;김영희
    • 한국정보통신학회논문지
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    • 제18권1호
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    • pp.115-122
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    • 2014
  • 본 논문에서는 eFuse OTP 메모리가 넓은 동작전압 영역을 갖도록 하기 위해서 V2V($=2V{\pm}10%$)의 regulation된 전압을 이용한 RWL 구동회로와 BL 풀-업 부하회로를 제안하므로 수 십 $k{\Omega}$의 post-program 저항을 센싱하면서 OTP 셀의 blowing되지 않은 eFuse를 통해 흐르는 읽기 전류를 $100{\mu}A$ 이내로 억제하여 신뢰성을 확보하였다. 그리고 OTP 셀 어레이 사이즈를 1행 ${\times}$ 32열과 4행 ${\times}$ 8열의 경우에 대해 OTP IP 크기를 비교한 결과 32비트 eFuse OTP의 레이아웃 면적은 각각 $735.96{\mu}m{\times}61.605{\mu}m$ ($=0.04534mm^2$), $187.065{\mu}m{\times}94.525{\mu}m$ ($=0.01768mm^2$)로 4행 ${\times}$ 8열의 32비트 eFuse OTP 사이즈가 1행 ${\times}$ 32열의 32비트 eFuse OTP 사이즈보다 더 작은 것을 확인하였다.

비냉각 열 영상 시트템용 BSCT $320{\times}240$ IR-FPA의 구현 (Implementation of BSCT $320{\times}240$ IR-FPA for Uncooled Thermal Imaging System)

  • 강대석;신경욱;박재우;윤동한;송성해;한명수
    • 대한전자공학회논문지SD
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    • 제39권11호
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    • pp.7-13
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    • 2002
  • 적외선 열 영상 system에서 가장 핵심이 되는 BSCT 320X240 IRFPA를 구현하였다. 검출기 module은 두 개의 부분, 즉 적외선 감지 pixel의 array와 감지된 신호를 읽어내는 ROIC로 구성된다. 50-${\mu}m$의 pitch와 95-%의 fill-factor를 만족하도록, laser scriber공정과 10-${\mu}m$ 크기의 ball을 갖는 micro bump공정을 적용하였다. ROIC는 선택된 신호를 읽어서 순차적으로 출력하게 설계되었으며, 단일 transistor amplifier, HPF, tunable LPF 그리고 clamp circuit를 삽입하여 SNR이 개선되도록 설계하였다. Detector와 ROIC의 결합으로 제작된 hybrid chip은 좀더 안정한 동작을 하도록 TEC가 내장된 ceramic package에 탑재하였다. 제작된 IRFPA sample은 원하는 특성을 만족하였으며, 특히 fill-factor, 탐지도, 반응도면에서 설계의 목표에 잘 근사함을 알 수 있었다.

CO2가스를 이용하여 증착된 터널층의 계면포획밀도의 감소와 이를 적용한 저전력비휘발성 메모리 특성 (Decrease of Interface Trap Density of Deposited Tunneling Layer Using CO2 Gas and Characteristics of Non-volatile Memory for Low Power Consumption)

  • 이소진;장경수;;김태용;이준신
    • 한국전기전자재료학회논문지
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    • 제29권7호
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    • pp.394-399
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    • 2016
  • The silicon dioxide ($SiO_2$) was deposited using various gas as oxygen and nitrous oxide ($N_2O$) in nowadays. In order to improve electrical characteristics and the interface state density ($D_{it}$) in low temperature, It was deposited with carbon dioxide ($CO_2$) and silane ($SiH_4$) gas by inductively coupled plasma chemical vapor deposition (ICP-CVD). Each $D_{it}$ of $SiO_2$ using $CO_2$ and $N_2O$ gas was $1.30{\times}10^{10}cm^{-2}{\cdot}eV^{-1}$ and $3.31{\times}10^{10}cm^{-2}{\cdot}eV^{-1}$. It showed $SiO_2$ using $CO_2$ gas was about 2.55 times better than $N_2O$ gas. After 10 years when the thin film was applied to metal/insulator/semiconductor(MIS)-nonvolatile memory(NVM), MIS NVM using $SiO_2$($CO_2$) on tunneling layer had window memory of 2.16 V with 60% retention at bias voltage from +16 V to -19 V. However, MIS NVM applied $SiO_2$($N_2O$) to tunneling layer had 2.48 V with 61% retention at bias voltage from +20 V to -24 V. The results show $SiO_2$ using $CO_2$ decrease the $D_{it}$ and it improves the operating voltage.

재가열 튀김유의 이화학적 특성과 전자코에 의한 향기 패턴 분석 (Physiochemical Properties of Repeated Deep-frying Oil and Odor Pattern Analysis by Electronic Nose System)

  • 김남숙;신정아;이기택
    • 동아시아식생활학회지
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    • 제16권6호
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    • pp.717-723
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    • 2006
  • Chemical characteristics of soybean oil after deep-frying with potato sticks (200 g, 10% w/w of soybean oil) were studied according to the 34 deep-frying times. After consecutive 34 deep-frying, total polyunsaturated FA contents was gradually decreased while the total saturated FA and trans FA were increased. Acid value and peroxide value were increased while iodine value decreased, respectively. The Hunter $L^{\ast}$ value decreased while each $a^{\ast}\;and \;b^{\ast}b$ value were gradually increased. Electronic nose equipped with 12 metal oxide sensors was used for the discrimination of odor pattern of frying oils against the times of deep-trying. The proportions of 1st and 2nd principal component analysis showed 75.97% and 21.23%, respectively. While 6 among total 12 sensors well responded to discrimination of odor in the repented frying oils, suggesting that the odor pattern of each oil after deep-frying would be discriminated against fresh soybean oil, especially after 14 times. From the results, electronic nose could differentiate the degree of quality deterioration of the repeated deep-frying oils.

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Current Spreading Layer와 에피 영역 도핑 농도에 따른 4H-SiC Vertical MOSFET 항복 전압 최적화 (Optimization of 4H-SiC Vertical MOSFET by Current Spreading Layer and Doping Level of Epilayer)

  • 안정준;문경숙;구상모
    • 한국전기전자재료학회논문지
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    • 제23권10호
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    • pp.767-770
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    • 2010
  • In this work, we investigated the static characteristics of 4H-SiC vertical metal-oxidesemiconductor field effect transistors (VMOSFETs) by adjusting the doping level of n-epilayer and the effect of a current spreading layer (CSL), which was inserted below the p-base region with highly doped n+ state ($5{\times}10^{17}cm^{-3}$). The structure of SiC VMOSFET was designed by using a 2-dimensional device simulator (ATLAS, Silvaco Inc.). By varying the n-epilayer doping concentration from $1{\times}10^{16}cm^{-3}$ to $1{\times}10^{17}cm^{-3}$, we investigated the static characteristics of SiC VMOSFETs such as blocking voltages and on-resistances. We found that CSL helps distribute the electron flow more uniformly, minimizing current crowding at the top of the drift region and reducing the drift layer resistance. For that reason, silicon carbide VMOSFET structures of highly intensified blocking voltages with good figures of merit can be achieved by adjusting CSL and doping level of n-epilayer.

5.8GHz 마이크로파 무선전력전송을 위한 원형 편파 배열 안테나 설계 (Design of Circularly Polarized Array Antenna for 5.8GHz Microwave Wireless Power Transmission)

  • 이성훈;손명식
    • 반도체디스플레이기술학회지
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    • 제17권2호
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    • pp.20-25
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    • 2018
  • In this paper, we have designed circularly polarized array antenna for 5.8GHz microwave wireless power transmission. To obtain high antenna gain, we studied a single patch antenna, a $2{\times}1$ array antenna, a $2{\times}2$ array antenna, a $2{\times}4$ array antenna, and a $4{\times}4$ array antenna. Commonly, characteristics of each antenna have a frequency of 5.8 GHz and Right Hand Circular Polarization(RHCP) of circular polarization. Also, the results were obtained with the design to each antenna that the return loss was less than -10dB and the axial ratio was less than 3dB. The gain of the antennas was 6.08dBi for a single patch antenna, 9.69dBi for a $2{\times}1$ array antenna, 12.99dBi for a $2{\times}2$ array antenna, 15.72dBi for a $2{\times}4$ array antenna and 18.39dBi for a $4{\times}4$ array antenna. When the elements of the array antenna were increased, it was confirmed that it increased by about 3dBi.

CMOS x-ray 라인 스캔 센서 설계 (Design of a CMOS x-ray line scan sensors)

  • 허창원;장지혜;김려연;허성근;김태우;하판봉;김영희
    • 한국정보통신학회논문지
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    • 제17권10호
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    • pp.2369-2379
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    • 2013
  • 본 논문에서는 의료영상 뿐만 아니라 비파괴검사 등에 활용되고 있는 CMOS x-ray 라인 스캔 센서를 설계하였다. x-ray 라인 스캔 센서는 512열${\times}$4행의 픽셀 어레이(pixel array)를 갖고 있으며, DC-DC 변환기(converter)를 내장하였다. Binning 모드를 이용하여 픽셀 사이즈가 $100{\mu}m$, $200{\mu}m$, $400{\mu}m$이 되도록 선택할 수 있도록 하기 위해 no binning 모드, $2{\times}2$ binning 모드와 $4{\times}4$ binning 모드를 지원하는 픽셀 회로를 새롭게 제안하였다. 그리고 power supply noise와 입력 common mode noise에 둔감한 이미지 신호인 fully differential 신호를 출력하도록 설계하였다. $0.18{\mu}m$ x-ray CMOS 이미지 센서 공정을 이용하여 설계된 라인 스캔 센서의 레이아웃 면적은 $51,304{\mu}m{\times}5,945{\mu}m$ 이다.

A Real-time Compact Structured-light based Range Sensing System

  • Hong, Byung-Joo;Park, Chan-Oh;Seo, Nam-Seok;Cho, Jun-Dong
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제12권2호
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    • pp.193-202
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    • 2012
  • In this paper, we propose a new approach for compact range sensor system for real-time robot applications. Instead of using off-the-shelf camera and projector, we devise a compact system with a CMOS image-sensor and a DMD (Digital Micro-mirror Device) that yields smaller dimension ($168{\times}50{\times}60mm$) and lighter weight (500g). We also realize one chip hard-wired processing of projection of structured-light and computing the range by exploiting correspondences between CMOS images-ensor and DMD. This application-specific chip processing is implemented on an FPGA in real-time. Our range acquisition system performs 30 times faster than the same implementation in software. We also devise an efficient methodology to identify a proper light intensity to enhance the quality of range sensor and minimize the decoding error. Our experimental results show that the total-error is reduced by 16% compared to the average case.

Design of Cellular Power Amplifier Using a SifSiGe HBT

  • Hyoung, Chang-Hee;Klm, Nam-Young;Han, Tae-Hyeon;Lee, Soo-Min;Cho, Deok-Ho
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1997년도 춘계학술대회 논문집
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    • pp.236-238
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    • 1997
  • A cellular power amplifier using an APCVD(Atmospheric Pressure Chemical Vapor Deposition)-grown SiGe base HBT of ETRI has been designed with a linear simulation CAD. The Si/SiGe HBT with an emitter area of 2$\times$8${\mu}{\textrm}{m}$$^2$typically has a cutoff frequency(f$_{T}$) of 7.0 GHz and a maximum oscillation frequency(f$_{max}$) of 16.1 GHz with a pad de-embedding A packaged power Si/SiGe HBT with an emitter area of 2$\times$8$\times$80${\mu}{\textrm}{m}$$^2$typically shows a f$_{T}$ of 4.7 GHz and a f$_{max}$ of 7.1 GHz at a collector current (Ic) of 115 mA. The power amplifier exhibits a Forward transmission coefficient(S21) of 13.5 dB, an input and an output reflection coefficients of -42 dB and -45 dB respectively. Up to now the III-V compound semiconductor devices hale dominated microwave applications, however a rapid progress in Si-based technology make the advent of the Si/SiGe HBT which is promising in low to even higher microwave range because of lower cost and relatively higher reproducibility of a Si-based process.ess.ess.

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