• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.3
• /
• pp.61-71
• /
• 2014

As the occupancy rate of the flash memory increases in the storage media market for the embedded system and the semi-conductor industry grows, the demand and supply of flash memory is increasing by a big margin. They are especially used in large quantity in the smart phones, tablets, PC, SSD and Soc(System on Chip) etc. The flash memory is divided into the NOR type and NAND type according to the cell arrangement structure and the NAND type is divided into the SLC(Single Level Cell) and MLC(Multi Level Cell) according to the number of bits that can be stored in each cell. Many tests have been performed on NOR type such as BIST(Bulit-In Self Test) and BIRA(Bulit-In Redundancy Analysis) etc, but there is little study on the NAND type. For the case of the existing BIST, the test can be proceeded using external equipments like ATE of high price. However, this paper is an attempt for the improvement of credibility and harvest rate of the system by proposing the BIST for the MLC NAND type flash memory of Finite State Machine structure on which the pattern test can be performed without external equipment since the necessary patterns are embedded in the interior and which uses the MLC NAND March(x) algorithm and pattern which had been proposed for the MLC NAND type flash memory.

• Proceedings of the KIEE Conference
• /
• 2001.11c
• /
• pp.376-379
• /
• 2001

In this paper, I design the control chip that controls inner test sequence of Logic Tester to test chip. Logic tester has the thirteen inner instructions to control test sequence in test. And these instructions are saved in memory with test pattern data. Control chip generates address and control signal such as read, write signal of memory. Before testing, necessary data such as start address, end address, etc. are written to inner register of control chip. When test started, control chip receives the instruction in start address and executes, and generates address and control signals to access tester' inner memory. So whole test sequence is controlled by making the address and control signal in tester's inner memory. Control chip designs instruction's execution blocks, respectively. So if inner instruction is added from now on, a revision is easy. The control chip will be made using FPGA of Xilinx Co. in future.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.2
• /
• pp.72-85
• /
• 2007

The development of memory design and process technology enabled the production of high density memory. However, this increased the complexity of the memory making memory testing more complicated, and as a result, it brought about an increase in memory testing costs. Effective memory test algorithm must detect various types of defects within a short testing time, and especially in the case of port memory test algorithm, it must be able to detect single port memory defects, and all the defects in the dual port memory. The March A2PF algorithm proposed in this paper is an effective test algorithm that detects all types of defects relating to the duel port and single port memory through the short 18N test pattern.

• Journal of IKEEE
• /
• v.5 no.1 s.8
• /
• pp.43-51
• /
• 2001

As the density of memories increases, unwanted interference between cells and coupling noise between bit-lines are increased. And testing high-density memories for a high degree of fault coverage can require either a relatively large number of test vectors or a significant amount of additional test circuitry. So far, conventional test algorithms have focused on faults between neighborhood cells, not neighborhood bit-lines. In this paper, a new test algorithm for neighborhood bit-line sensitive faults (NBLSFs) based on the NPSFs(Neighborhood Pattern Sensitive Faults) is proposed. And the proposed algorithm does not require any additional circuit. Instead of the conventional five-cell or nine-cell physical neighborhood layouts to test memory cells, a three-cell layout which is minimum size for NBLSFs detection is used. Furthermore, to consider faults by maximum coupling noise by neighborhood bit-lines, we added refresh operation after write operation in the test procedure(i.e.,$write{\rightarrow}\;refresh{\rightarrow}\;read$). Also, we show that the proposed algorithm can detect stuck-at faults, transition faults, coupling faults, conventional pattern sensitive faults, and neighborhood bit-line sensitive faults.

• The Transactions of the Korean Institute of Electrical Engineers D
• /
• v.54 no.6
• /
• pp.403-408
• /
• 2005

As the increasing integrity of VLSI, the BIST(Built-In Self Test) is used as an effective method to test chips. Generally the pseudo-random test pattern generation is used for BIST. But it requires too many test patterns when there exist random This paper proposes and presents a new efficient network architecture for Reflective Memory System (RMS). A time to copy shared-data among nodes effects critically on the entire performance of the RMS. In this paper, the recent researches about the RMS are investigated and compared. The device named Topology Conversion Switch(TCS) is introduced to realize the proposed network architecture. One of the RMS based industrial control networks, Ethernet based Real-time Control Network (ERCnet), is adopted to evaluate the performance of the proposed network architecture for RMS.

• KIPS Transactions on Software and Data Engineering
• /
• v.5 no.12
• /
• pp.623-634
• /
• 2016

Most of existing frequent pattern mining methods address time efficiency and greatly rely on the primary memory. However, in the era of big data, the size of real-world databases to mined is exponentially increasing, and hence the primary memory is not sufficient enough to mine for frequent patterns from large real-world data sets. To solve this problem, there are some researches for frequent pattern mining method based on disk, but the processing time compared to the memory based methods took very time consuming. There are some researches to improve scalability of frequent pattern mining, but their processes are very time consuming compare to the memory based methods. In this paper, we present PPFP as a novel disk-based approach for mining frequent itemset from big data; and hence we reduced the main memory size bottleneck. PPFP algorithm is based on FP-growth method which is one of the most popular and efficient frequent pattern mining approaches. The mining with PPFP consists of two setps. (1) Constructing an IFP-tree: After construct FP-tree, we assign index number for each node in FP-tree with novel index numbering method, and then insert the indexed FP-tree (IFP-tree) into disk as IFP-table. (2) Mining frequent patterns with PPFP: Mine frequent patterns by expending patterns using stack based PUSH-POP method (PPFP method). Through this new approach, by using a very small amount of memory for recursive and time consuming operation in mining process, we improved the scalability and time efficiency of the frequent pattern mining. And the reported test results demonstrate them.

• Journal of IKEEE
• /
• v.12 no.1
• /
• pp.65-74
• /
• 2008

One of the popular methods used for pattern classification is the MBR (Memory-Based Reasoning) algorithm. Since it simply computes distances between a test pattern and training patterns or hyperplanes stored in memory, and then assigns the class of the nearest training pattern, it is notorious for memory usage and can't learn additional information from new data. In order to overcome this problem, we propose an incremental learning algorithm (iMPA). iMPA divides the entire pattern space into fixed number partitions, and generates representatives from each partition. Also, due to the fact that it can not learn additional information from new data, we present iMPA which can learn additional information from new data and not require access to the original data, used to train. Proposed methods have been successfully shown to exhibit comparable performance to k-NN with a lot less number of patterns and better result than EACH system which implements the NGE theory using benchmark data sets from UCI Machine Learning Repository.

• Journal of Korea Foundry Society
• /
• v.9 no.1
• /
• pp.58-66
• /
• 1989

The effect of heat treating temperature and ${\alpha}$ phase In the ${\beta}$ phase matrix were investigated for ${\beta}-CuZnAl$ shape memory alloys by tension test, fatigue test, and shape memory effect test. After heat treatment at $677^{\circ}C$, $750^{\circ}C$, $800^{\circ}C$ and $850^{\circ}C$ for 10 min. respectively, static fracture stress(${\sigma}_f$), fatigue fracture stress(${\tau}_{max}$) at $10^6$ cycle, and elongation(${\epsilon}_f$) was $24.2kg/mm^2$, $17.21kg/mm^2$ and 11.8%, respectively. As heat treating temperature decreased, fracture surfaces of the specimens were changed from the intergranular to the transgranular fracture mode. Especially, the a phase precipitated in the ${\beta}$ phase matrix had an effect on crack propagation and the fracture surface was characterized by dimple-like pattern when crack propagated in transgranular cracking mode. Precipitation of the ${\alpha}$ phase in the ${\beta}$ phase matrix lowered the transformation temperature by $10^{\circ}C$, and about 2.5 vol.% ${\alpha}$ phase did not affect the shape memory effect examined by the bending test.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.9
• /
• pp.85-95
• /
• 2004

As the design complexity increases, it is a major problem that the size of test pattern is large and power consumption is high in scan, especially system-on-a-chip(SoC), with the automatic test equipment(ATE). Because static compaction of test patterns heads to higher power for testing, it is very hard to reduce the test pattern volume for low power testing. This paper proposes an efficient compression/decompression algorithm based on run-length coding for reducing the amount of test data for low power testing that must be stored on a tester and be transferred to SoC. The experimental results show that the new algorithm is very efficient by reducing the memory space for test patterns and the hardware overhead for the decoder.

• Sleep Medicine and Psychophysiology
• /
• v.26 no.1
• /
• pp.16-22
• /
• 2019

Objectives: The objective of this study was to investigate the correlation between insufficient sleep and visuospatial memory in adolescents using a computerized neurocognitive function test. Methods: A total of 103 high school students (26 males and 77 females; mean age $17.11{\pm}8.50years$) without a serious psychiatric problem was recruited. All subjects were requested to complete a self-report questionnaire about weekday total sleep time and weekend total sleep time. The epworth sleepiness scale (ESS) and the beck depression inventory (BDI) were administered to measure daytime sleepiness and symptoms of depression. Seven subsets of the Cambridge Neuropsychological test automated battery were examined to assess visuospatial memory. Results: After controlling for age, sex, ESS, and BDI, longer weekend total sleep time was correlated with poor performance on delayed matching to sample (r = -0.312, p = 0.002) and immediate recall on pattern recognition memory (r = -0.225, p = 0.025). Increased weekend catch-up sleep time was correlated with poor performance of delayed matching to sample (r = -0.236, p = 0.018), immediate recall on pattern recognition memory (r = -0.220, p = 0.029), and delayed recall on pattern recognition memory (r = -0.211, p = 0.036) after controlling for age, sex, ESS, and BDI. Conclusion: This study showed that increased weekend catch-up sleep time reflecting insufficient weekday sleep were associated with poor performance in delayed recall tasks of visual memory. This finding suggests that insufficient sleep during adolescence might produce a decline of visuospatial memory.