• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.367-370
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• 2000

It is shown that $I_{DDQ}$ testing is very useful for shipping fault-free CMOS ICs. However, test time of $I_{DDQ}$ testing is extremely larger than one of logic testing. In this paper, a new test input sequence generation methodology is proposed to reduce the test time of $I_{DDQ}$ testing. At first, it is Shown that $I_{DDQ}$ test time Will be denominated by charge supply current for load capacitance of gates whose output logic values are changed by test input vector application and the charge current depends on input sequence of test vectors. After that, a test input sequence generation methodology is proposed. The feasibility is checked by some experiments.riments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.11
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• pp.2255-2263
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• 1994

Protocol conformance testing consists of procedures to observe an output and to check a transition state of the Implementation Under Test considered as a black box by applying an input. There are several methods to check the transition state such as Unique Input/Output(UIO) sequence. Distinguishing Sequence(DS) and Characterization Set(CS). Particularly, as a test method for a state having no UIO sequence, Partial UIO sequence method can be considered. In this paper, three properties which can be found among Partial UIO sequence and a modified algorithm using these properties are suggested.

• Journal of Korea Multimedia Society
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• v.1 no.1
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• pp.109-119
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• 1998

This paper describes a research result on automatic generation of Abstract Test Suite from INAP protocol in formal specifications by applying many existing related algorithms such as Rural Chinese Postman Tour and UIO sequence concepts. We use the I/O FSM generated from SDL specifications and a characterizing sequence concepts. We use the I/O FSM generated from SDL specifications and a characterizing sequence, called UIO sequence, is defined for the I/O FSM. The UIO sequence is combined with the concept of Rural Chinese Postman tour to obtain an optimal test sequence. It also proposes an estimation methodology of the fault courage for the Test Suite obtained by our method and their translation into the standardized test notation TTCN.

• ETRI Journal
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• v.19 no.4
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• pp.363-388
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• 1997

This paper describes a research result on automatic generation of abstract test cases from formal specifications by applying many related algorithms and techniques such as the testing framework, rural Chinese postman tour and unique input output sequence concepts. In addition, an efficient algorithm for verifying the strong connectivity of the reference finite state machine and the concept of unique event sequence are explained. We made use of several techniques to from an integrated framework for abstract test case generation from LOTOS and SDL specifications. A prototype of the proposed framework has been built with special attention to real protocol in order to generate the executable test cases in an automatic way. The abstract test cases in tree and tabular combined notation (TTCN) language will be applied to the TTCN compiler in order to obtain the executable test cases which re relevant to the industrial application.

• The KIPS Transactions:PartD
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• v.17D no.5
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• pp.337-346
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• 2010

Timing diagram is popularly utilized for the reason of its advantages; it is convenient for timing diagram to describe behavior of system and it is simple for described behaviors to recognize it. Various techniques are needed to test systems described in timing diagram. One of them is a technique to derive the system into a certain condition under which a test case is effective. This paper proposes a technique to automatically generate the test input sequence to reach the condition for systems described in timing diagram. It requires a proper input set which satisfy transition condition restricted by input waveform and timing constraints to generate a test input sequence automatically. To solve the problem, this paper chooses an approach utilizing the linear programming, and solving procedure is as follows: 1) Get a Timing diagram model as an input, and transforms the timing diagram model into a linear programming problem. 2) Solve the linear programming problem using a linear programming tool. 3) Generate test input sequences of a timing diagram model from the solution of linear programming problem. This paper addresses the formal method to drive the linear programming model from a given timing diagram, shows the feasibility of our approach by prove it, and demonstrates the usability of our paper by showing that our implemented tool solves an example of a timing diagram model.

• Journal of KIISE
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• v.44 no.7
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• pp.674-679
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• 2017

In big-data environments wherein large amounts of text documents are produced daily, titles are very important clues that enable a prompt catching of the key ideas in documents; however, titles are absent for numerous document types such as blog articles and social-media messages. In this paper, a title-generation model for which sequence-to-sequence RNNs with attention and copying mechanisms are employed is proposed. For the proposed model, input sentences are encoded based on bi-directional GRU (gated recurrent unit) networks, and the title words are generated through a decoding of the encoded sentences with keywords that are automatically selected from the input sentences. Regarding the experiments with 93631 training-data documents and 500 test-data documents, the attention-mechanism performances are more effective (ROUGE-1: 0.1935, ROUGE-2: 0.0364, ROUGE-L: 0.1555) than those of the copying mechanism; in addition, the qualitative-evaluation radiative performance of the former is higher.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.4
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• pp.325-332
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• 2017

In this paper, a survey of test sequence generation methods for testing the conformance of a protocol implementation to its specification is presented. The best known methods proposed in the literature are called transition tour, distinguishing sequence, characterizing sequence, and unique input/output sequence. Also, several variants of the above methods are introduced. Applications of these methods to the finite state machine model are discussed. Then, comparative analysis of the methods is made in terms of test sequence length. Finally, conclusions are given as follows. The T-method produces the shortest test sequence, but it has the worst fault coverage. The W-method tends to produce excessively long test sequences even though its fault coverage is complete. The problem with the DS-method is that a distinguishing sequence may not exist. The UIO-method is more widely applicable, but it does not provide the same fault coverage as the DS-method.

• The Transactions of the Korea Information Processing Society
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• v.4 no.2
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• pp.552-562
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• 1997

This paper proposes a formal method on confromance testing for INAP(AIN) test sequence generation by optimization technique.In order to implement and prove the dffectiveness of the proposed method,we specify the SRSM of INAP protocol SRF in SDL and generate I/O FSM by using our S/W tool. We generate an opti-mal test sequence by applying our method our method to this reference I/O FSM. We prove experimentally that the length of the generated test sequence by our method is more effective and shorter(i.e 32% improved)than the one geverated by UIO method,and estimate that The test coverage space of our test sequence is larger that of UIO method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.9
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• pp.1395-1403
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• 1993

Protocol conformance is crucial to inter-operability and cost effective computer communication. Given a protocol specification, the task of checking whether an inplementation conforms to the specification is called conformance testing. The efficiency and fault coverage of conformance testing are largely dependent on how test cases are chosen. Some states may have more one UIO sequence when the protocol is represented by FSM (Finite State Machine). The length of test sequence can be minimized if the optimal test sequences are chosen. In this paper, we construct the depth-tree to find the maximum overlapping among the test sequence. By using the resulting depth-tree, we generate the minimum-length test sequence. We show the example of the minimum-length test sequence obtained by using the resulting depth-tree.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.9
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• pp.1854-1866
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• 1997

This paper proposes a new test case generation technique for a nondeterministic finite state machine by improving the existing UIO sequence generation method. First, a new conformance relationis defined, which is one of prerequisites for automatic test case generation. Because fof the nondeterministic property of torpocols, the output of the systems under test is not known deterministically to the tester. Therefore, tree-like test case generation method is introduced for adaptive testing, in which the next input is selected after observing the previous output. Since the test cases are generated with regarding the inputs and outputs as separate events and are represented in tree notation, the test cases are easily converted into TTCN, the international standard test suite specification language.