• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.293-296
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• 2012

SOC test methodology in ultra deep submicron (UDSM) technology with reasonable test time and cost has begun to satisfy high quality and reliability of the product. A novel hierarchical test architecture using IEEE standard 1149.1, 1149.7 and 1500 compliant facilities is proposed for the purpose of supporting flexible test environment to ensure SOC test methodology. Each embedded core in a system-on- a-chip (SOC) is controlled by test access ports (TAP) and TAP controller of IEEE standard 1149.1 as well as tested using IEEE standard 1500. An SOC device including TAPed cores is hierarchically organized by IEEE standard 1149.7 in wafer and chip level. As a result, it is possible to select/deselect all cores embedded in an SOC flexibly and reduce test cost dramatically using star scan topology.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.360-360
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• 2010

반도체 산업은 지속적인 design rule 감소로 인해 직접도 및 Pin Count가 점점 증가함에 따라 보증해야할 회로의 수와 기능이 더불어 증가하고 있으며, 그 중 Test Cost 감소 방법 확보가 시급하게 되었다. 이에 따라 Test Cost 감소와 직결된 Test Time 감소 방법이 다양하게 제시되고 연구되고 있다. 본 논문은 Test Time의 한 부분인 반도체 검사 장비 (Automatic Test Equipment)의 효율적인 제어 방법을 제공함으로써, 관련 분야의 이해를 돕고자 한다.

• The Journal of Asian Finance, Economics and Business
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• v.8 no.1
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• pp.767-780
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• 2021

The purpose of this research is to analyze the effect of financial elements (asset growth, liability growth, equity growth, revenue growth, and profit growth) on stock price performance and to analyze the growth of Corporate Social Responsibility (CSR) costs as a moderating effect. The technique analysis used is regression analysis. Samples in this analysis are manufacturing firms listed on the Indonesian Stock Exchange (IDX) for the period 2014-2018. The use of regression models for hypothesis testing must fulfill several applicable assumptions such as Normality Test, Heteroscedasticity Test, Multicollinearity Test, Autocorrelation Test, Model Fit Test, Determination Coefficient Test, and Hypothesis Test. Data analysis used two research models, namely model 1 and model 2. Model 1 is without the moderating variable, and model 2 is with the moderating variable, that is, CSR cost growth. Based on the result of the regression analysis, it can be inferred that the asset, revenue, and profit growth have a positive impact on stock price results. Liabilities and equity growth do not affect stock price performance. Operating expense growth has a significant effect on price performance. CSR cost growth can moderate the effect of growth in financial statement elements on stock price performance but is not significant.

• Journal of Korean Society for Quality Management
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• v.39 no.1
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• pp.71-77
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• 2011

In the fields of reliability application, the most commonly used test methods for reliability qualification are zero failure tests since they require fewer test samples and less test time compared to other test methods that guarantee the same reliability with a given confidence level. An economic zero failure test plan is developed that minimizes the total cost related to perform a life test to guarantee a specified reliability of a product with a given confidence level and a numerical example is provided to illustrate the use of the proposed test method.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.18 no.8
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• pp.635-640
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• 2006

An optimizer has been applied for the optimal design of pipe diameters in the pipe flow network problems. Pipe network flow analysis, which is developed separately, is performed within the interface for the optimization algorithm. A pipe network is chosen for the test, and optimizer GenOpt is applied with Holder-Mead-O'Niell's simplex algorithm after solving the network flow problem by the Newton-Raphson method. As a result, optimally do-signed pipe diameters are successfully obtained which minimize the total design cost. Design cost of pipe flow network can be considered as the sum of pipe installation cost and pump operation cost. In this study, a practical and efficient solution method for the pipe network optimization is presented. Test system is solved for the demonstration of the present optimization technique.

• Transactions of the Korean Society of Automotive Engineers
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• v.11 no.2
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• pp.182-189
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• 2003

We have found that the damage of the front part for a vehicle and that of the rear part for a vehicle are the majority of frequency experienced by the traffic accidents. In conventional bumper system was designed by safety standard regulation at low speed crash. For example there are 2.5 mile and 5 mile bumper. The conventional bumper system was the crash from max 5.5 mile to 3 mile low speed occurs most frequently and results in the highest rate of repairing cost in statistically. On this study, in order to check the damageability and repairability of gas tube bumper system RCAR 15 km/h 40 % offset frontal crash test was adopted in low speed and we have a gas tube bumper parts test and vehicle test with gas tube bumper, we can find gas tube bumper system definitely can improve the damageability and repairability of the vehicles and contribute to down the repairing cost.

• The Journal of Fisheries Business Administration
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• v.51 no.3
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• pp.17-31
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• 2020

The purpose of this study is to identify economic situation on scale of tuna distant longline fishery by analyzing its economies of scale using the cost function. To analyze its economics of scale, the deep-sea fishing statistics were used from 2012 to 2016. In detail, the number of panels for estimating the cost function was 68 tuna distant longline vessels from 2012 to 2016, and the total number of observations over the five years were 340. As a final model, the two-way fixed effect model based on the translog cost function was adopted through the F test, the Breusch-Pagan test and the Hausman test. As a result of the analysis, it was found that tuna distant longline fishery between 2012 and 2014 was diseconomies of scale, the fishery between 2015 and 2016 was economies of scale. However, the economic indicators of the scale from 2012 to 2016 were almost close to zero, indicating that the constant returns to scale, the optimal scale, were reached. Therefore, in the situation where the amount of fishery resources in the world continues to decrease, it is necessary to prepare a method to obtain economic benefits through scale maintenance and reduction rather than indiscriminate scale expansion.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.20 no.2
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• pp.97-105
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• 2008

This paper presents simulated and experimental test results of optimal control algorithm for an encapsulated ice thermal storage system with full capacity chiller operation. The algorithm finds an optimal combination of a chiller and/or a storage tank operation for the minimum total operation cost through a cycle of charging and discharging. Dynamic programming is used to find the optimal control schedule. The conventional control strategy of chiller-priority is the baseline case for comparing with the optimal control strategy through simulation and experimental test. Simulation shows that operating cost for the optimal control with chiller on-off operation is not so different from that with chiller part load capacity control. As a result from the experimental test, the optimal control operation according to the simulated operation schedule showed about 14 % of cost saving compared with the chiller-priority control.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.65-73
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• 2007

This paper introduces design-for-test (DFT) techniques for low-cost system-on-chip (SoC) test. We present a Scan-Test method that controls IEEE 1500 wrapper thorough IEEE 1149.1 SoC TAP (Test Access Port) and design an at-speed test clock generator for delay fault test. Test cost can be reduced by using small number of test interface pins and on-chip test clock generator because we can use low-price automated test equipments (ATE). Experimental results evaluate the efficiency of the proposed method and show that the delay fault test of different cores running at different clocks test can be simultaneously achieved.

• ETRI Journal
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• v.37 no.4
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• pp.787-792
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• 2015

To accomplish a high-speed test on low-speed automatic test equipment (ATE), a new instruction-based fully programmable memory built-in self-test (BIST) is proposed. The proposed memory BIST generates a highspeed internal clock signal by multiplying an external low-speed clock signal from an ATE by a clock multiplier embedded in a DRAM. For maximum programmability and small area overhead, the proposed memory BIST stores the unique sets of instructions and corresponding test sequences that are implicit within the test algorithms that it receives from an external ATE. The proposed memory BIST is managed by an external ATE on-the-fly to perform complicated and hard-to-implement functions, such as loop operations and refresh-interrupts. Therefore, the proposed memory BIST has a simple hardware structure compared to conventional memory BIST schemes. The proposed memory BIST is a practical test solution for reducing the overall test cost for the mass production of commodity DDRx SDRAMs.