• 전자공학회논문지A
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• 제33A권5호
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• pp.212-221
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• 1996

A CMOS comparator is designed for low voltage and low power operations. The proposed comparator consists of a preadmplifier followed by a regenerative latch. The preasmplifier reduces the power consumption to a half with the power-down mode and the dynamic offsets of the latch, which is affected by each device mismatch, is statistically analyzed. The circuit is designed and simulated using a 0.8.mu.m n-well CMOS process and the dissipated power is 0.16mW at a 20MHz clock speed based on a 3V supply.

• 대한전자공학회논문지
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• 제15권4호
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• pp.26-32
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• 1978

실리콘 태양전지의 수명을 예측하기 위하여 1 MeV electron radiation으로 인한 실리콘 손상을 조사 연구하였다. 그 결과 흑형 실리콘에 있어서는 거의 안정상태의 손상에 이르렀음을 보았다.

• 대한전자공학회논문지
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• 제19권1호
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• pp.35-40
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• 1982

마이크로프로세서는 공학분야에서 점차 보편화 되고 있다. 본 논문에서는 제어계의 감쇠상수 ζ을 변화하는 제어기를 마이크로프로세서로 구현해 본 것이다. 결과는 응답시간면에서 긍정적으로 개선되었음을 볼 수 있었다.

• 전자공학회논문지A
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• 제32A권12호
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• pp.159-165
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• 1995

A gate-recessed structure is introduced to SOI MOSFET's in order to increase the source-to-drain breakdown voltage. A significant increase in the breakdown voltage is observed compared with that of a planar single source/drain SOI MOSFET without inducing the appreciable reduction of the current drivability. We have analyzed the origin of the breakdown voltage improvement by the substrate current measurements and 2-D device simulations, and shown that the breakdown voltage improvement is caused by the reductions in the impact ionization rate and the parasitic bipolar current gain.

• 대한전자공학회논문지
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• 제24권3호
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• pp.472-477
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• 1987

In order to prevent the short-channel effects due to threshold voltage adjustment implantation in conventional n+ doped silicon gate process, a new approach involving automatic doping of polycide by boron during source and drain implantation is introduced. P-MOSFET devece fabricated by theis approach shows improved short channel characteristics than conventional device with n+ doped gate. Some concerns of adopting this approach in CMOS technology are addressed togetheer with some suggestions.

• 대한전자공학회논문지
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• 제25권2호
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• pp.176-181
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• 1988

In this paper, the LPC speech synthesizer with Multipulsse excitation is implemented using general-purpose DSP \ulcornerD7720. As the driving function for synthesis filter is used in the amplitude and position of pulse, the Voice/Unvoice decision and pitch period detectioncan be excluded. The synthesizer is implemented with DSP device which is operated on the interrupt mehtod with main computer and on the DMA mehtod with D/A converter. The comparision of synthetic and original waveform, alogn with the listening test, proves the validity of this system.

• 전자공학회논문지D
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• 제35D권3호
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• pp.18-27
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• 1998

Molecular dynamicsinvestigations of ion implantation considering point defect generation were performed with ion energies in the range of ~1keV, Simulation starts perfect diamond cubic lattice site. Stillinger-Weber potential and ZBL potential were used to calculate forces between atoms. We have simulated slowing-down of ion velocity, ion trajectory and coupled-coing between ion and silicon. We also discussed distribution of point defect using rdial distribution function. We found that interstitial produced by ion bombardment mainly formed interstitial cluster.

• 전자공학회논문지A
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• 제30A권3호
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• pp.88-94
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• 1993

In this paper, a simple Ebers-Moll Model for the heterojunction bipolar transistor is presented. Using the model structure for the npn type HBT, the current-voltage characteristics was analyzed. And from the obtained terminal currents, the Ebers-Moll equations were derived. Then substituting the physical parameters for heterojunction to those for homojunction, this model would be used to analyze the characteristics of single and/or duble heterojunction HBT's. And directly relating model parameters to device parameters, it would be also used to optimize the characteristics of HBT's. The simulated results using this model were in good agreement with experimental data.

• 전자공학회논문지A
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• 제32A권11호
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• pp.79-85
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• 1995

In this paper, an epi layer and a device structure for InP/InGaAs p-i-n/HBT OEIC is designed for a receiving frontend of high speed optical communications. A 3 stage transimpedance circuit using the p-i-n/HBT device is also designed by SPICE simulations for a high sensitivity including ISI noises at a given bit rate. Our simulations show that the Personick's assumption which is not commonly satisfied have estimated a photoreceiver sensitivity too high, so thus we have to also consider ISI noises in OCIC receiver designs.

• 전자공학회논문지B
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• 제33B권3호
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• pp.56-61
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• 1996

In this paper, new buck converter of a TV power system is presented. First, we devised a revised driving circuit for an emitter-coupled type buck converter, by which it is possible to reduce the material cost of transformers and voltage stress of power device. Secondly, we adopted a hybrid oscillation technique. When TV system is in off-stage, initial standby power which is necessary for remote controllable TV system is supplied by self-oscillating mode. Main power which is necessry in TV system bing on state is provided by an externally triggered oscillating mode. The switching frequency is synchronized to the oscillating frequency of horizontal deflection in TV, by which we can reduce picture noises and the size of power transformer. Thirdly, a simple error amplifier is inserted to the feed-back loop to keep the output voltage constant which means pulse width modulatio mode is added in driving part of power device. Finally, we showed by experiments that our proposed converter performs well enough to be close to the theoretically predicted values.