• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.12
• /
• pp.65-71
• /
• 1996

A novel lateral field emitter triode has been designed and fabricated. It has self-vacuum environmets and low turn-on voltage, so that the chief problems of previous field emission devices such as additional vacuum sealing process and high turn-on voltage are settled. An in-situ vaccum encapsulation empolying recessed cavities by isotropic RIE (reactive ion etch) method and an electron beam evaporated molybdenum vacuum seals are implemented to fabricate the new field emitter triode. The device exhibits low turn-on voltage of 7V, stabel current density of 2.mu.A/tip at V$_{AC}$ = 30V, and high transconductance (g$_{m}$) of 1.7$\mu$S at V$_{AC}$ = 22V. The superb device characteristics are probably due to sub-micron dimension device structure and the pencil type lateral cathode tip employing upper and lower LOCOS oxidation.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.32A no.1
• /
• pp.103-110
• /
• 1995

Trench-Gate SOI LIGBT with improved latch-up capability has been proposed and verified by MEDICI simulation. The new SOI LIGBT exhibits 6 time larger latch-up capability of the new device is almost preserved independent of lifetime. the large latch-up capability of the new SOI LIGBT may be realized due to the fact that the hole current in the new device would bypass through the shorted cathode contact without passing the p-well region under the n+ cathode. Forward voltage drop is increased by 25% when a epi thickness is 6$\mu$m. However, the increase of the forward voltage is negligible when the epi thickness is increased to 10$\mu$m. It is found that the swithcing time of the new device is almost equal to the conventional devices. Evaluated breakdown voltage of proposed SOILIGBT is 250 V and that of the conventional SOI LIGBT is 240 V, where the thickness of the vuried oxide and n- epi is 3$\mu$m and 6$\mu$m, respectively.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.12
• /
• pp.91-99
• /
• 1994

We used CMOS current mirror and differenial amplifier to find out how the degradation of each devices in circuit affect total circuit performance. The devices in circuit wer degraded by hot-carrier generated during circuit operation and total circuit performance were changed according to the change of each device parameters. To examine the circuit performance phenomena of current mirror, we analyzed three diffent kinds of current mirrors and made correlation model between circuit performance and stressed device parameters, and compare hot-carrier immunity of these circuits. Also we analyzed how the performance of differential amplifier degraded from the initial value after hot-carrier stress incircuit operations.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.34D no.11
• /
• pp.37-47
• /
• 1997

Utilizing 2-dimensional device simulations incorporating lattic eheating models, we analyzed in detail the DC breakdown characterisics of NMOS trasistors with different structures, which are commonly used as ESD protection transistors. The mechanism leading to device failure resulting from electrostatic discharge was explained by analyzing the 1st and 2nd breakdown characteristics of LDD devices. Also a criteria for more robust designs of NMOS transistor structures against ESD was suggested by examining the characteristics changes with changes in structural parameters such as the LDD doping concentration, the drain junction depth, the distance between source/drain contacts, and the source junction area.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.30A no.9
• /
• pp.38-45
• /
• 1993

In this study, the degradation characteristics of drain output resis-tance was described due to hot electron effects. An semi-empirical model for the degraded drain output resistance was derived from the measured device characteristics. The suggested model was verified from the measured data and the device parameter dependence was also analyzed. The degradation of drain output resistance was increased with stress time and had linear relationship with the degradation of drain current. The device lifetime which was defined by failure criteria of drain output resistance (such as $\Delta$ro/roo=5%) was equivalent to that of failure criteria of drain current (such as $\Delta$ID/ID=5%)

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.27 no.2
• /
• pp.98-104
• /
• 1990

A study of the operation of surface and buried mode PMOSFET's is condusted. Using device with different channel length and channel implant dosage, threshold voltage lowering, transcon-diuctance and subthreshold characteristics of surface mode PMOFET are compared with those of buried mode MPOSFET. From the results, the surface channel device were more resistant to short channel effect than the buried channel device.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.32A no.7
• /
• pp.69-76
• /
• 1995

A new device structure has been developed for p-i-n switches. In this structure, the phosphorus-diffused n$^{+}$ layter adjacent to the boron-doped anode is used to short the p$^{+}$ anode-channel(i-region). This change in the anode electrode structure results in a significant improvement in the threshold voltage-to-holding voltage($V_{Th}/V_{h}$) ratio, which is due to the suppression of the hold injection from the anode by the n$^{+}$ layer. The shorted anode p-i-n devices of a 100 .mu.m channel length show an extremely high threshold voltage in the 250~300 V range and a low holding voltage in the 5~9 V range. These features of the device are expected to acdelerate their practical application to power switching circuits.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.3
• /
• pp.89-95
• /
• 1996

In this ppaer, temeprature dependent transport and heat transport models have been incorperated to the two dimensional device simulator SNU-2D provides a solid bse for nonisothermal device simulation. As an example to study the nonisothermal problem. we consider SOI MOSFET's I-V characteristics have been simulated and compared with the measurements. It is shown that negative slopes in the Ids-Vds characteristics are casused by the temperature dependence of the saturation velocity and the degradation of the temperature dependence mobility. Also it is shown that the kink effect occurs when impact ionization near the drain produces a buildup of holes in this isolated device island, and the hysteresis is caused by the creation of holes in the channel and their flow to the source.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.24 no.5
• /
• pp.818-822
• /
• 1987

Gate capacitances have been measured directly on small-geometry MOSFET's with the drain voltage as a parameter for various channel lengths and for p and n channel types and the characteristics have been compared with each other. The influence of 'hot carrier effect' of short channel devices on capaciatance has been compared with long channel devices. The results show that gate capacitance characteristics of short channel device deviate from those of long channel device. The accuracy of the measurement system is less than a few femto Farad, and the minimum geometry (W/L) of device for which reliable measurement can be obtained is 6/3.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.29A no.3
• /
• pp.72-78
• /
• 1992

The Silicon vertical Hall devices are fabricated using standard bipolar process and characterized in terms of the Hall voltage, sensitivities, and offset voltage. The Hall voltage and sensitivity of the devices showed good linearity with respect to the magnetic flux density and reverse supply voltage Vr. The sensitivity of device with P$^{+}$ isolation dam has been increased up to 1.2 times compared to that of device without the dam. With the condition of V$_{r}$=-5.0[V], B=0.4[T] and I$_{sup}$=1.0[mA], the Hall voltage and sensitivity of the device with P$^{+}$ isolation dam were about 29[mV] and 74[V/AT], respectively. These vertical Hall devices can be used as the adjustable magnetic fields sensor.