• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.9
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• pp.89-95
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• 1994

BaTiO$_{x}$ thin film as insulator and ZnS:Mn film as phosphour layer for thin film electrouminescent device have been deposited by thermal evalporation and dependence of electrical and opeical characeristics have been studied. The optimum deposition conditions for the BaTiO$_{x}$ thin film are such that BaTiO$_{3}$/TiO$_{2}$ mixing ratio was 0.7, sub strate temperature was 100 $^{\circ}C$ and annealing time was 1 hour at 300 $^{\circ}C$. In this case, the dielectric constant of BaTiO$_{x}$ thin film fabricated under those optimum conditions was 26, and for AnS:Mn thin films, the crystallization was done well and the deposition rate was 1300 $\AA$/min when substrate temperature was 200$^{\circ}C$. Thin film Electroluminescent devices were fabricated using BaTiO$_{x}$ and AnS:Mn thin films. The luminescence threshold voltage of device was 41.5 V and brightness was 1.2${\mu}W/cm^{2}$ at appied voltage of 50 V.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.9
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• pp.121-127
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• 1994

The capability for application of rf magnetron sputterred and post annealed BaTiO$_{3}$ thin films in dielectrics AC drived TFELD(thin film electroluminescent device) was investigated. The dielectric constant of the thin films slightly increased up to about 25 with increase fothe post annealing temperature in the range of 210$^{\circ}C$-480$^{\circ}C$. The dielectric loss was about 0.005-0.01 except for the high frequency range above 100kHz and nearly independent on post annealing temperature. The BaTiO$_{3}$ thin film used for TFELD was annealed at 480.deg. C and Si$_{3}$N$_{4}$ thin film was inserted between BaTiO$_{3}$, lower dielecrics and ZnS:Mn, phosphor layer for stable driving of the device and for fear of interdiffusion. Regardless of the frequency of the applied sine wave voltage, the threshold voltage of the prepared TFELD was 65volt and saturated brightness was about 3000cd/m$^{2}$ at 130volt(2kHz sine wave), 65volt above V$_{TH}$.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.11
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• pp.99-104
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• 1993

We analyzed the D.I. water used in wet cleaning process of semiconductor device manufacturing both at the D.I. water plant and at the wafer cleaning bath to detect the impurity source of D.I. water contamination. This shows that the quantity of impurity is related to the resistivity of D.I. water, and we found that the cleanliness of the wafer surface processed in D.I. water bath was affected by the degree of the ionic impurity contamination. So we evaluated the cleaning effect as different method for Fe ion, having the best adsoptivity on wafer surface. Moreover the temperature effect of the D.I. water is investigated in case of anion in order to remove the chemical residue after wet process. In addition to the control of D.I. water resistivity, chemical analysis of impurity control in D.I. water should be included and a suitable cleaning an drinsing method needs to be investigated for a high yielding semiconductor device.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.11
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• pp.126-134
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• 1990

In order to implement high-speed data acquistion system in CMOS VLSI technology, means must be found to overcome the relatively low transconductance and large device mismatch characteristic of MOS device. Because of these device limitations, circuit design approaches tradition-ally used in high-speed bipolar analog-to-digital converter(ADC) are suited to CMOS implementation. Also the design of VLSI CMOS comparator wherein voltage comparision is accomplished by means of a pipelined cascade RSA (Regenerative Sense Amplifier). So, in this paper we designed the A/D converter incorporates the pipelined CMOS comparator.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.3
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• pp.76-87
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• 1993

We present a self-consistent, 2-dimensional solution of the Poisson and Sch rodinger equation based on the finite difference method with a nonuniform mesh size for a AlGaAs/GaInAs/GaAs HEMT devide. During the interative self-consistent calculation, however, we calculate Schrodinger equation only a some region of device, not a fully region in order to save the moemory and the speed-up of computation, and then use the approximated data for the other region using by a interpolation method with a given values. Also we adopt the proper matrix transformation method that allows preservation of the symmetric, form of the discretized Schrodinger equation, even with the use of a nonumiform mesh size, therefor, can reduce the computation time. We calculate the wavefunction, eigenstates and the electron concentration uat channel layer nder the thermal equilibrium and the biased conditions, respectively. Also,these parameters are used to solve 2-dimensional tdistribution of potential in he entire region of device. It is proved that the method is very efficient in finding eigenstages extending over relatively large spatial area without loss of accuracy. So, it can be used rather easily in any sarbitrary modulation doped utucture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.11A
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• pp.1128-1137
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• 2007

Recently, according to being advanced internet, mobile communication technique, Telematics environment which users in vehicle can use internet service in LAN(Local Area Network) via mobile device has being realized. In this paper, we propose the remote user authentication protocol to solve these issues. Additionally, we use biometrics(fingerprint) for our user authentication protocol cause it can provide to avoid critical weakness that can be lost, stolen, or forgotten and to make authentication easily. In our user authentication protocol, to protect the biometric we use session key which is generated from master key distributed in our key distribution protocol. In particular, we propose secure protocol between APs considering weakness of security in mobile environment. Based on implementation of our proposed protocol, we conform that our proposed protocols are secure from various attack methods and provide real-time authentication.

• Journal of Korea Spatial Information System Society
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• v.10 no.1
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• pp.41-49
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• 2008

This paper presents a data analysis method for the taxi telematics system which generates a greate deal of location history data. By the record consist of the basic GPS receiver-generated fields, device-added fields such as taxi operation status, and framework-attached fields such as matched link Identifier and position ratio in a link, each taxi can be represented by a state diagram. The transition and the state definition enable us to efficiently extract such information as pick-up time, pick-up distance, dispatch time, and dispatch distance. The analysis result can help to verify the efficiency of a specific taxi dispatch algorithm, while the analysis framework can invite a new challenging service including future traffic estimation, trajectory clustering, and so on.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.2
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• pp.6-12
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• 1998

Thin film SOI(Silicon-on-insulator) device offer unique advantages such as reduction in short channel effects, improvement of subthreshold slope, higher mobility, latch-up free nature, and so on. But these devices exhibit floating-body effet such as current kink which inhibits the proper device operation. In this paper, the SOI NMOSFET with a T-type gate structure is proposed to solve the above problem. To simulate the proposed device with TSUPREM-4, the part of gate oxide was considered to be 30nm thicker than the normal gate oxide. The I-V characteristics were simulated with 2D MEDICI. Since part of gate oxide has different oxide thickness, the gate electric field strength is not same throughout the gate and hence the impact ionization current is reduced. The current kink effect will be reduced as the impact ionization current drop. The reduction of current kink effect for the proposed device structure were shown using MEDICI by the simulation of impact ionization current, I-V characteristics, and hole current distribution.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.123-129
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• 1996

LDD structure is widely accepted in fabricating short channel MOSFETs due to reduced short channel effect originated form lower drain edge electric field. However, modeling of the LDD device is troublesome because the analysis methods of LDD region known are either too complicated or inaccurate. To solve the problem, this paper presents a nonlinear resistance model for the LDD region based on teh fact that the electron mobility changes with positive gate bias because accumulation layer of electrons is formed at the surface of the LDD region. To prove the usefulness of the model, single source/drain and LDD nMOSFETs were fabricated with 0.35$\mu$m CMOS technolgoy. For the fabricated devices we have measured I$_{ds}$-V$_{gs}$ characteristics and compare them to the modeling resutls. First of all, we calculated channel and LDD region mobility from I$_{ds}$-V$_{gs}$ characteristics of 1050$\AA$ sidewall, 5$\mu$m channel length LDD NMOSFET. Then we MOSFET and found good agreement with experiments. Next, we use calculated channel and LDD region mobility to model I$_{ds}$-V$_{gs}$ characteristics of LDD mMOSFET with 1400 and 1750$\AA$ sidewall and 5$\mu$m channel length and obtained good agreement with experiment. The single source/drain device characteristic modeling results indicates that the cahnnel mobility obtained form our model in LDD device is accurate. In the meantime, we found that the LDD region mobility is governed by phonon and surface roughness scattering from electric field dependence of the mobility. The proposed model is useful in device and circuit simulation because it can model LDD device successfully even though it is mathematically simple.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.9
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• pp.54-61
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• 1998

A new Triple well structure is proposed for improved latch-up immunity at deep submicron CMOS device. Optimum latch-up immunity process condition is established and analyzed with varying ion implantation energy and amount of dose and also compared conventional twin well structure. Doping profile and structure are investigated using ATHENA which is process simulator, and then latch-up current is calculated using ATLAS which is device simulator. Two types of different process are affected by latch-up characteristics and shape of doping profiles. Finally, we obtained the best latch-up immunity with 2.5[mA/${\mu}{m}$] trigger current using 2.5 MeV implantation energy and 1$\times$10$^{14}$ [cm$^{-2}$ ] dose at p-well