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A Scheduling Approach with Component Selection

  • Harashima, Katsumi;Satoh, Hisashi;Hiro, Daisuke;Kutsuwa, Toshiro
    • Proceedings of the IEEK Conference
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    • 2000.07a
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    • pp.399-402
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    • 2000

  • The reduction of chip area and delay is important purpose of Scheduling in High-Level Synthesis. This paper presents a scheduling approach with component selection. After obtaining a initial schedule taking only single-functional u-nits, the component selection of our approach attempts the reduction of chip area and/or delay by the selection more suitable components in a component library using Simulated Annealing.

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