• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.1 s.343
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• pp.41-48
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• 2006

An anti-collision algorithm is very important in the RFID system because it decides tag identification time and tag identification accuracy. We propose improved anti-collision algorithms using Bin slot in RFID system. In the proposed algorithms, if the reader memorizes the Bin slot information, it can reduce the repetition of unnecessary PingID command and the time to identify tags. If we also use ScrollA11ID command in the proposed algorithm, the reader knows the sequence of collided E bits. Using this sequence, the reader can reduce the repetition of PingID command and tag identification time. We analyze the performance of the proposed anti-collision algorithms and compare the performance of the proposed algorithms with that of the conventional algorithm. We also validate analytic results using simulation. According to the analysis, for the random tag n, comparing the proposed algorithms with the conventional algorithm, the performance of the proposed algorithms is about $130\%$ higher when the number of the tags is 200. And for the sequential tag ID, the performance of the conventional algorithm decreases. On the contrary, the performance of the proposed algerian using ScrollA11ID command is about $16\%$ higher than the case of using random tag ID.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.7
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• pp.1497-1501
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• 2005

Branch instructions which make the sequential instruction flow changed cause pipeline stalls in microprocessor. The pipeline hazard due to branch instructions are the most serious problem that degrades the performance of microprocessors. Branch target buffer predicts whether a branch will be taken or not and supplies the address of the next instruction on the basis of that prediction. If the hanch target buffer predicts correctly, the instruction flow will not be stalled. This leads to the better performance of microprocessor. In this paper, the architecture of a ta8 memory that branch target buffer and TLB can share is presented. Because the two tag memories used for branch target buffer and TLB each is replaced by single combined tag memory, we can expect the smaller chip size and the faster prediction. This shared tag architecture is more advantageous for the microprocessors that uses more bits of address and exploits much more instruction level parallelism.

• Journal of the Korea Society of Computer and Information
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• v.18 no.11
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• pp.87-97
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• 2013

In the RFID system, multiple tags respond in the process of identifying multiple tags in the reader's interrogation zone, resulting in collisions. Tag collision occurs when two or more tags respond to one reader, so that the reader cannot identify any tags. These collisions make it hard for the reader to identify all tags within the interrogation zone and delays the identifying time. In some cases, the reader cannot identify any tags. The reader needs the anti-collision algorithm which can quickly identify all the tags in the interrogation zone. The proposed algorithm efficiently divides tag groups through an efficient separation to respond, preventing collisions. Moreover, the proposed algorithm identifies tags without checking all the bits in the tags. The prediction with efficient separation reduces the number of the requests from the reader.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.10
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• pp.1491-1497
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• 2013

Radio frequency identification (RFID) is an important and essential components of ubiquitous computing, with the development of wireless communication technologies and mobile computing environment. Recently, RFID becomes the mainstream application that helps fast handling and uniquely identifying the physical objects. It utilizes the electromagnetic energy for data transmission from a tag to a reader in the presence of arbitrary interference and noise. In order to employ the portable mobile RFID reader, a tag-collision problem between two or more adjacent tags should be considered. In this paper, we present the operation of RFID system in which numerous tags are present in the interrogation zone of a single reader at the same time. Since there may exist a number of tagged objects in the narrow area, multiple RFID tags may interfere each other, caused to degrade the data reliability and efficiency of the RFID system. In order to suppress interference signals from multiple neighboring tags, we present an application of Gold code for RFID communication system, which uses spread spectrum technique. In this RFID system, data bits are spreaded in each tags with the unique Gold code and the spreaded data bits are despreaded in the reader with the same Gold code. The performance analysis of the considered RFID anti-collision system is illustrated via computer simulation examples.

• The KIPS Transactions:PartA
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• v.14A no.2
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• pp.117-124
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• 2007

In this paper we present a translation lookaside buffer (TLB) system with low power consumption for embedded processors. The proposed TLB is constructed as multiple banks, each with an associated block buffer and a corresponding comparator. Either the block buffer or the main bank is selectively accessed on the basis of two bits in the block buffer (tag buffer). Dynamic power savings are achieved by reducing the number of entries accessed in parallel, as a result of using the tag buffer as a filtering mechanism. The performance overhead of the proposed TLB is negligible compared with other hierarchical TLB structures. For example, the two-cycle overhead of the proposed TLB is only about 1%, as compared with 5% overhead for a filter (micro) TLB and 14% overhead for a same structure without continuos accessing distinction algorithm. We show that the average hit ratios of the block buffers and the main banks of the proposed TLB are 95% and 5% respectively. Dynamic power is reduced by about 95% with respect to with a fully associative TLB, 90% with respect to a filter TLB, and 40% relative to a same structure without continuos accessing distinction algorithm.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.788-791
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• 2010

We design 64-bit ROM IP for RFID tag chips using printed CMOS non-volatile memory IP design technology for a printed CMOS process. The proposed 64-bit ROM circuit is using ETRI's $0.8{\mu}m$ CMOS porocess, and is expected to reduce process complexity and cost of RFID tag chips compared to that using a conventional silicon fabrication based on a complex lithography process because the poly layer in a gate terminal is using printing technology of imprint process. And a BL precharge circuit and a BL sense amplifier is not required for the designed cell circuit since it is composed of a transmission gate instead of an NMOS transistor of the conventional ROM circuit. Therefore an output datum is only driven by a DOUT buffer circuit. The Operation current and layout area of the designed ROM of 64 bits with an array of 8 rows and 8 columns using $0.8{\mu}m$ ROM process is $9.86{\mu}A$ and $379.6{\times}418.7{\mu}m^2$.

• Journal of Internet Computing and Services
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• v.10 no.2
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• pp.133-141
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• 2009

A tag collision problem occurs when many tags are placed in a interrogation zone in RFID system. A tag collision problem is one of core issues and various protocols have been proposed to solve the collision problems. Generally tree-based protocols generate unique prefixes and identify tags with them as quick as possible. In this paper, we propose the QT-BCS protocol which decreases the identification time by reducing the number of query-response. The QT-BCS protocol makes a prefixes using time slot and bit change sensing unit. This protocol compares the current bit of tags until the current bit is differ from the previous one. When this occurs, all of the bits scanned so far are transferred to slot-0 and slot-1 depending on the first bit value in Reader. Consequently, this method can reduce the number of queries by tracing prefixes easily. Simulation result shows QT-BCS is more efficient in identifying tags than Query Tree and 4-ary Query Tree protocol.

• Journal of Korea Society of Industrial Information Systems
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• v.17 no.3
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• pp.19-26
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• 2012

To resist the relay attacks in RFID system, it is commonly used RFID distance bounding protocols using the round trip time measurement for 1 bit challenge and response between a reader and a tag. If the success probability of relay attacks for the 1 bit challenge and response can be reduced in these protocols, it is possible to make an efficient distance bounding protocol. In this paper, we propose an efficient RFID distance bounding protocol based on 2 bit challenge and response which is modified the RFID distance bounding protocol proposed by Hancke and Khun based on 1 bit challenge and response. The success probability of relay attack for the proposed protocol is (7/16)n for the n times of challenge and response, which is much lower than (3/4)n given by Hancke and Khun's protocol.

• IE interfaces
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• v.22 no.3
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• pp.278-286
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• 2009

The anti-collision algorithms to identify a number of tags in real-time in RFID systems are divided into the anti-collision algorithms based on the Framed slotted ALOHA that randomly select multiple slots to identify the tags, and the anti-collision algorithms based on the Tree-based algorithm that repeat the questions and answer process to identify the tags. In the hybrid algorithm which is combined the advantages of these algorithms, tags are distributed over the frames by selecting one frame among them and then identified by using the Query tree frame by frame. In this hybrid algorithm, however, the time of identifying all tags may increase if many tags are concentrated in a few frames. In this study, to improve the performance of the hybrid algorithm, we suggest an improved algorithm that the tags select a specific group of frames based on the earlier bits of the tag ID so that the tags are distribute equally over the frames. By using the simulation and mathematical analysis, we show that the suggested algorithm outperforms traditional hybrid algorithm from the viewpoint of the number of queries per frame and the time of identifying all tags.

• The KIPS Transactions:PartA
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• v.14A no.1 s.105
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• pp.47-54
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• 2007

In this paper we present a translation lookaside buffer (TLB) system with low power consumption for imbedded processors. The proposed TLB is constructed as multiple banks, each with an associated block buffer and a corresponding comparator. Either the block buffer or the main bank is selectively accessed on the basis of two bits in the block buffer (tag buffer). Dynamic power savings are achieved by reducing the number of entries accessed in parallel, as a result of using the tag buffer as a filtering mechanism. The performance overhead of the proposed TLB is negligible compared with other hierarchical TLB structures. For example, the two-cycle overhead of the proposed TLB is only about 1%, as compared with 5% overhead for a filter (micro)-TLB and 14% overhead for a same structure without continuos accessing distinction algorithm. We show that the average hit ratios of the block buffers and the main banks of the proposed TLB are 95% and 5% respectively. Dynamic power is reduced by about 95% with respect to with a fully associative TLB, 90% with respect to a filter-TLB, and 40% relative to a same structure without continuos accessing distinction algorithm.