• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.05a
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• pp.771-773
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• 2014

본 논문에서는 장거리 레이더용 차량 충돌 방지 77-GHz CMOS 믹서를 제안한다. 이러한 회로는 2볼트 전원전압에서 동작하며, 저 전압 전원 공급에서도 높은 변환 이득과 낮은 변환 손실 및 낮은 잡음지수를 가지도록 설계되어 있다. 제안한 회로는 TSMC $0.13{\mu}m$ 혼성신호/고주파 CMOS 공정($f_T/f_{MAX}=120/140GHz$)으로 설계하였다. 전체 칩 면적을 줄이기 위해 수동형 인덕터 대신 전송선(Transmission Line) 을 이용하였다. 본 논문에서 설계한 믹서는 약 5.2dB의 우수한 변환이득 특성과 2.1dBm의 우수한 IIP3 특성을 보였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.467-468
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• 2019

본 논문은 차량용 장거리 레이더를 위한 저 위상잡음 77GHz CMOS 전압제어발진기를 제안한다. 이러한 회로는 낮은 위상잡음을 가지도록 설계되어 있고, 1.5볼트 전원에서 동작한다. 제안한 회로는 TSMC $0.13{\mu}m$ 고주파 CMOS 공정으로 설계하였다. 제안한 회로는 최근 발표된 연구결과에 비해 저 위상잡음, 저 전력 및 적은 면적 특성을 보였다.

• Electronics and Telecommunications Trends
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• v.38 no.3
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• pp.86-97
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• 2023

The outbreak of the novel coronavirus disease in 2020 caused a global semiconductor supply shortage and disruption in the production of devices such as iPhones owing to China's quarantine lockdown. Thus, Apple is diversifying its production bases from China to countries like India and Vietnam. The company is also accelerating semiconductor development to guarantee a stable supply, reduce design costs, and customize semiconductors with high quality and outstanding specifications for their products to outperform devices that use general-purpose semiconductors. Following the mobile application processor, Apple is releasing world-class semiconductors, such as the M1 and M2 chips that play the role of central processing units.

• ETRI Journal
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• v.45 no.4
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• pp.690-703
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• 2023

Multistage amplifiers have become appropriate choices for high-speed electronics and data conversion. Because of the large number of high-impedance nodes, frequency compensation has become the biggest challenge in the design of multistage amplifiers. The new compensation technique in this study uses two differential stages to organize feedforward and feedback paths. Five Miller loops and a 500-pF load capacitor are driven by just two tiny compensating capacitors, each with a capacitance of less than 10 pF. The symbolic transfer function is calculated to estimate the circuit dynamics and HSPICE and TSMC 0.18 ㎛. CMOS technology is used to simulate the proposed five-stage amplifier. A straightforward iterative approach is also used to optimize the circuit parameters given a known cost function. According to simulation and mathematical results, the proposed structure has a DC gain of 190 dB, a gain bandwidth product of 15 MHz, a phase margin of 89°, and a power dissipation of 590 ㎼.

• Electronics and Telecommunications Trends
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• v.39 no.3
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• pp.98-106
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• 2024

Advanced packaging is emerging as a core technology owing to the increasing demand for multifunctional and highly integrated semiconductors to achieve low power and high performance following digital transformation. It may allow to overcome current limitations of semiconductor process miniaturization and enables single packaging of individual devices. The introduction of advanced packaging facilitates the integration of various chips into one device, and it is emerging as a competitive edge in the industry with high added value, possibly replacing traditional packaging that focuses on electrical connections and the protection of semiconductor devices.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.2
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• pp.26-36
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• 2008

Due to the differential and low voltage swing, Low Voltage Differential Signaling(LVDS) has been widely used for high speed data transmission with low power consumption. This paper proposes new LVDS I/O interface circuits for more than 1.3 Gb/s operation. The LVDS receiver proposed in this paper utilizes a sense amp for the pre-amp instead of a conventional differential pre-amp. The proposed LVDS allows more than 1.3 Gb/s transmission speed with significantly reduced driver output voltage. Also, in order to further improve the power consumption and noise performance, this paper introduces an inductance impedance matching technique which can eliminate the termination resistor. A new form of unfolded impedance matching method has been developed to accomplish the impedance matching for LVDS receivers with a sense amplifier as well as with a differential amplifier. The proposed LVDS I/O circuits have been extensively simulated using HSPICE based on 0.35um TSMC CMOS technology. The simulation results show improved power gain and transmission rate by ${\sim}12%$ and ${\sim}18%$, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.19-27
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• 2007

This paper presents power supply-insensitive Gbps low power LVDS I/O circuits. The proposed LVDS I/O has been designed and simulated using 1.8V, $0.18\;{\mu}m$ TSMC CMOS Process. The LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and an output stage with the switched capacitor common mode feedback(SC-CMFB). The differential phase splitter generates a pair of differential signals which provides a balanced duty $cycle(50{\pm}2%)$ and phase difference$(180{\pm}0.2^{\circ})$ over a wide supply voltage range. Also, $V_{OD}$ voltage is 250 mV which is the smallest value of the permissible $V_{OD}$ range for low power operation. The output buffer maintains the required $V_{CM}$ within the permissible range$(1.2{\pm}0.1V)$ due to the SC-CMFB. The receiver covers a wide input DC offset $range(0.2{\sim}2.6\;V)$ with 38 mV hysteresis and Produces a rail-to-rail output over a wide supply voltage range. Beside, the designed receiver has 38.9 dB gain at 1 GHz, which is higher than conventional receivers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.15-22
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• 2006

In this paper, 1.8V 8-bit 500MSPS Low-power CMOS Digital-to-Analog Converter(DAC) for UWB(Ultra Wide Band) Communication Systeme is proposed. The architecture of the DAC is based on a current steering 6+2 full matrix type which has low glitch and high linearity. In order to achieve a high speed and good performance, a current cell with a high output impedance and wide swing output range is designed. Further a thermometer decoder with same delay time and low-power switching decoder for high efficiency performance are proposed. The proposed DAC was implemented with TSMC 0.18um 1-poly 6-metal N-well CMOS technology. The measured SFDR was 49dB when the output frequency was 50MHz at 500MS/s sampling frequency. The measured INL and DNL were 0.9LSB and 0.3LSB respectively. The DAC power dissipation was 20mW and the effective chip area was $0.63mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.15-23
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• 2009

Microprocessors, which need correct arithmetic operations, have been the subject of in-depth research in relation to soft errors. Of the existing microprocessor devices, the memory cell is the most vulnerable to soft errors. Moreover, when soft errors emerge in a memory cell, the processes and operations are greatly affected because the memory cell contains important information and instructions about the entire process or operation. Users do not realize that if soft errors go undetected, arithmetic operations and processes will have unexpected outcomes. In the field of architectural design, the tool that is commonly used to detect and correct soft errors is the error check and correction code. The Itanium, IBM PowerPC G5 microprocessors contain Hamming and Rasio codes in their level-2 cache. This research, however, focuses on huge server devices and does not consider power consumption. As the operating and threshold voltage is currently shrinking with the emergence of high-density and low-power embedded microprocessors, there is an urgent need to develop ECC (error check correction) circuits. In this study, the in-output data of the level-2 cache were analyzed using SimpleScalar-ARM, and a 32-bit H-matrix for the level-2 cache of an embedded microprocessor is proposed. From the point of view of power consumption, the proposed H-matrix can be implemented using a schematic editor of Cadence. Therefore, it is comparable to the modified Hamming code, which uses H-spice. The MiBench program and TSMC 0.18 um were used in this study for verification purposes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.2
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• pp.47-55
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• 2012

A discrete-time(DT) filter with high-order temporal moving average(TMA) using actively-weighted charge sampling is proposed in this paper. To obtain different weight of sampled charge, the variable transconductance OTA is used prior to charge sampler, and the ratio of charge can be effectively weighted by switching the control transistors in the OTA. As a result, high-order TMA operation can be possible by actively-weighted charge sampling. In addition, the transconductance generated by the OTA is relatively accurate and stable by using the size ratio of the control transistors. The high-order TMA filter has small size, increased voltage gain, and low parasitic effects due to the small amount of switches and sampling capacitors. It is implemented in the TSMC $0.18-{\mu}m$ CMOS process by TMA-$2^2$. The simulated voltage gain is about 16.7 dB, and P1dB and IIP3 are -32.5 dBm and -23.7 dBm, respectively. DC current consumption is about 9.7 mA.