• Journal of the Korea Society of Computer and Information
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• v.18 no.12
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• pp.1-9
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• 2013

Even though the multiple pages TLB are effective in improving the performance, a conventional method with OS support cannot utilize multiple page sizes in user application. Thus, we propose a new multiple-TLB structure supporting multiple page sizes for high performance and low power consumption without any operating system support. The proposed TLB is organised as two parts of a S-TLB(Small TLB) with a small page size and a L-TLB(Large TLB) with a large page size. Both are designed as fully associative bank structures. The S-TLB stores small pages are evicted from the L-TLB, and the L-TLB stores large pages including a small page generated by the CPU. Each one bank module of S-TLB and L-TLB can be selectively accessed base on particular one and two bits of the virtual address generated from CPU, respectively. Energy savings are achieved by reducing the number of entries accessed at a time. Also, this paper proposed the simple 1-bit LRU policy to improve the performance. The proposed LRU policy can present recently referenced block by using an additional one bit of each entry on TLBs. This method can simply select a least recently used page from the L-TLB. According to the simulation results, the proposed TLB can reduce Energy * Delay by about 76%, 57%, and 6% compared with a fully associative TLB, a ARM TLB, and a Dual TLB, respectively.

• IEMEK Journal of Embedded Systems and Applications
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• v.17 no.1
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• pp.59-65
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• 2022

Virtual memory is used as the method to ensure the safety of the system through memory protection in the real-time system. TLB miss caused by using virtual memory makes the real-time system WCET more pessimistically. TLB lockdown can be applied as a method to improve this problem. However, processors with limited TLB lockdown entries, a selection criterion is needed to efficiently utilize the TLB lockdown entry. In this paper, the most frequently accessed virtual pages in the process are applied to the TLB lockdown by analyzing memory profiling. The results showed that micro data TLB miss stall cycle and main data TLB miss stall cycle of the processor decreased by at least 4.7% and up to 29.7%.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.4
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• pp.232-243
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• 2002

There are many methods for improving TLB (translation lookaside buffer) performance, such as increasing the number of entry in TLB, supporting large page or multiple page sizes. The best way is to support multiple page sizes, but any operating system doesn't support multiple page sizes in user mode. So, we propose the new structure of TLB supporting two pages to obtain the effect of multiple page sizes with high performance and at low cost without operating system support. we propose a new TLB structure supporting two page sizes dynamically and selectively for high performance and low cost design without any operating system support. For high performance, a promotion-TLB is designed by supporting two page sizes. Also in order to attain low power consumption, a banked-TLB is constructed by dividing one fully associative TLB space into two sub-fully associative TLBs. These two banked-TLB structures are integrated into a banked-promotion TLB as a low power and high performance TLB structure for embedded processors. According to the results of comparison and analysis, a similar performance can be achieved by using fewer TLB entries and also power consumption can be reduced by around 50% comparing with the fully associative TLB.

• The Transactions of the Korea Information Processing Society
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• v.3 no.1
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• pp.118-126
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• 1996

Memory hierarchy is a useful mechanism for improving the memory access speed and making the program space larger by layering the memories and separating program spaces from memory spaces. However, it needs at least two memory accesses for each data reference : a TLB(Translation Lookaside Buffer) access for the address translation and a data cache access for the desired data. If the cache size increases to the multiplication of page size and the cache associativity, it is difficult to access the TLB with the cache in parallel, thereby making longer the critical timing path in the processor. To achieve such parallel accesses, we present the hybrid mapped TLB which combines a direct mapped TLB with a very small fully-associative mapped TLB. The former can reduce the TLB access time. while the latter removes the conflict misses from the former. The trace-driven simulation shows that under given workloads the proposed TLB is effective even when a fully-associative mapped TLB with only four entries is added because the effects of its increased misses are offset by its speed benefits.

• Proceedings of the Korean Information Science Society Conference
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• 2000.04a
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• pp.42-44
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• 2000

TLB 성능을 높이기 위한 기존의 3가지 주요 연구방향은, TLB 엔트리 계수를 최대한 증대 시키는 방법, 페이지 크기(page size)를 크게 증대 시키는 방법, 다중 페이지 크기(multiple page sizes)을 지원하는 방법 등의 연구가 제시되어 왔다. 이러한 방법들 중 다중 페이지 크기를 지원하는 방법이 가장 우수한 성능을 제공하는 방법이지만, 이작 어떠한 운영체제(operting system)도 다중 페이지를 사용자(user) 영역까지 지원하고 있지는 않은 상태이다. 따라서 다중 페이지의 효과를 살리기 위해 운영체제의 도움 없이 이중 페이지를 지원하면서 낮은 가격(low cost)으로 높은 성능(high performance) 향상을 보일 수 있는 새로운 듀얼(dual) TLB 구조와 운영 방법을 제안하고자 한다. 제안하는 듀얼 TLB 구조는 작은 페이지 크기( small page size)를 지원하는 완전 연관TLB와 큰 페이지 크기(large page size)를 지원하는 완전 연관TLB로 구성된다. 제시된 구조는 기존의 많은 엔트리 개수를 지원하는 TLB와의 성능 비교분석 결과를 통해 볼 때, 작은 엔트리 개수를 가지면서도 거의 같은 성능을 보임을 알 수 있다. 또한 동일 한 TLB 면적 크기로 기존 방식의 접근 실패율을 90%정도 감소시키는 성능을 제시하였다.

• The Transactions of the Korea Information Processing Society
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• v.5 no.3
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• pp.620-632
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• 1998

This paper introduces a new teehniquc for reducing the compulsory misses of software-managed TLBs by prefetching necessary TLB entries before being used. This technique is not inherently limited to specific applications. The key of this scheme is to perform the prefetch operations to update the TLB entries before first accesses so that TLB misses can be avoided. For the identifications of the prefctch pages, the new classification is introduced, which is based 0n the view of an object code execution. Then, the algorithms and the implementation technique arc described. Using a quantitative analysis, the proposed scheme is evaluated to prove that it is a useful technique for the perronnall~~ ~nhan~"ment of the S/W managed TLBs. in addition, it is discussed that reducing the miss rate by the prefeteh scheme reduces the total miss penalty and bus traffics in S/W-managed TLBs.

• Journal of Chest Surgery
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• v.32 no.2
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• pp.164-170
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• 1999

Background: The diffuse infiltrative lung disease often requires biopsy for its final diagnosis. Unlike the limited exposure that can be achieved through small thoracotomy incisions in open lung biopsy technique, the thoracoscopic approach allows visualization and biopsy of nearly entire surface of the lung without morbidity of large standard thoracotomy. The purpose of this study was to compare the diagnostic efficacy and operative safety of thoracoscopic lung biopsy(TLB) with open lung biopsy(OLB) in the diagnosis of diffuse infiltrative lung disease. Material and Method: From March 1993 to August 1997, 81 patients were referred for diagnostic lung biopsy. 51 of them underwent standard open lung biopsy and the remaining 30 patients underwent thoracoscopic lung biopsy. Result: Mean operative time was 63 minutes for TLB and 79 minutes for OLB (p=0.04). The volume of biopsy specimen was not different between two groups(TLB 7.8 cm3, OLB 6.9 cm3 : p=0.72) and the diagnostic accuracy of each methods was comparable (TLB 100%, OLB 96%). The duration of hospital stay was significantly less in TLB (TLB 13days, OLB 22days : p=0.01). The duration of parenteral narcotics administration was also less for TLB(TLB 2.5days, OLB 5.2days, p=0.05). Meanwhile, the duration of chest tube drainage, the frequency of parenteral narcotic injection were not significantly different between two groups. Complications occurred in 2 among the TLB patients (6.67%) and 4 among the OLB patients (7.84%). There was no operative mortality in both groups. Conclusion: We concluded that TLB is a good alternative procedure to OLB in the diagnosis of diffuse infiltrative lung disease with lower morbidity and comparable diagnostic accuracy.

• The KIPS Transactions:PartA
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• v.14A no.1 s.105
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• pp.47-54
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• 2007

In this paper we present a translation lookaside buffer (TLB) system with low power consumption for imbedded processors. The proposed TLB is constructed as multiple banks, each with an associated block buffer and a corresponding comparator. Either the block buffer or the main bank is selectively accessed on the basis of two bits in the block buffer (tag buffer). Dynamic power savings are achieved by reducing the number of entries accessed in parallel, as a result of using the tag buffer as a filtering mechanism. The performance overhead of the proposed TLB is negligible compared with other hierarchical TLB structures. For example, the two-cycle overhead of the proposed TLB is only about 1%, as compared with 5% overhead for a filter (micro)-TLB and 14% overhead for a same structure without continuos accessing distinction algorithm. We show that the average hit ratios of the block buffers and the main banks of the proposed TLB are 95% and 5% respectively. Dynamic power is reduced by about 95% with respect to with a fully associative TLB, 90% with respect to a filter-TLB, and 40% relative to a same structure without continuos accessing distinction algorithm.

• Proceedings of the Korean Information Science Society Conference
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• 2011.06a
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• pp.555-558
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• 2011

하드웨어의 발전으로 인하여 한 머신에 장착되는 물리 메모리의 크기가 점차로 커지고 있으며, 가상화 기술과 같은 서버 통합 워크로드가 일반화됨에 따라 개별 응용프로그램의 working set size 또한 증가하고 있다. 하지만 가상주소에 대한 물리주소 변환의 cache인 TLB(Translation Look-aside Buffer)의 커버리지는 물리 메모리 크기가 커짐에 따라 점차 줄어들어 TLB miss가 발생하여 메모리 접근이 느려질 가능성이 더욱 높아지고 있다. 본 논문에서는 계층적 비트맵을 사용하는 TLB 표현 방법을 이용하여 TLB 커버리지를 높이는 하드웨어적인 기법을 제안하고, 이에 적합한 운영체제 기법을 제안한다.

• The KIPS Transactions:PartA
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• v.14A no.2
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• pp.117-124
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• 2007

In this paper we present a translation lookaside buffer (TLB) system with low power consumption for embedded processors. The proposed TLB is constructed as multiple banks, each with an associated block buffer and a corresponding comparator. Either the block buffer or the main bank is selectively accessed on the basis of two bits in the block buffer (tag buffer). Dynamic power savings are achieved by reducing the number of entries accessed in parallel, as a result of using the tag buffer as a filtering mechanism. The performance overhead of the proposed TLB is negligible compared with other hierarchical TLB structures. For example, the two-cycle overhead of the proposed TLB is only about 1%, as compared with 5% overhead for a filter (micro) TLB and 14% overhead for a same structure without continuos accessing distinction algorithm. We show that the average hit ratios of the block buffers and the main banks of the proposed TLB are 95% and 5% respectively. Dynamic power is reduced by about 95% with respect to with a fully associative TLB, 90% with respect to a filter TLB, and 40% relative to a same structure without continuos accessing distinction algorithm.