• Title/Summary/Keyword: THD+N

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A Study on Hight Efficiency Inverter Ballast using Microprocessor (마이크로프로세서를 사용한 고효율 인버터 안정기에 관한 연구)

  • ;鄭載倫
    • The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.13 no.2
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    • pp.220-220
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    • 1999
  • This paper describes the high efficiency inverter ballast circuit using very cheap microprocessor, which has been developed by the author. A variety of soft-switching techniques have been proposed to reduce the switching losses and EMI problems that occur with higher switching frequencies in switched inverter ballast. The inverter ballast circuit, which employs a temperature sensing circuits has been also proposed to improve starting performance of the fluorescent lamps. That is, the inverter ballast circuit, which employs a soft-starting circuit and soft-switching techniques to implement the power factor correction and to mitigate of power-loss and increase a life time of the fluorescent lamps, has become an attractive performance for ballasting the fluorescent lamps. In this paper, the operation and the control of the inverter ballast are described in detail and experimental results are presented. As the experimental results, when environment temperature is at -40℃, the inverter ballast circuit has low THD(4.8%) of the input current and large power factor(98%) of the lamp current. The proposed improved ballast circuit appears to be a good performance for ballasting fluorescent lamps.

The Effects of Training for Computer Skills on Outcome Expectations , Ease of Use , Self-Efficacy and Perceived Behavioral Control

  • Lee, Min-Hwa
    • Proceedings of the Korea Society for Industrial Systems Conference
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    • 1996.10a
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    • pp.29-48
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    • 1996
  • Previous studies on user training have largely focused on assessing models which describe the determinants of information technology usage or examined theeffects of training, on user satisfaction, productivity, performance and so on. Scant research efforts have been made, however, to examine those effects of training by using theoretical models. This study presented a conceptural model to predict intention to use information technology and conducted an experimentto understand how training for computer skill acquisition affects primary variables of the model. The data were obtained from 32 student subjects of an experimental group and 31 students of a control group, and the information technology employed for this study was a university's electronic mail system. The study results revealed that attitude toward usage and perceived behavioral control helped to predict user intentions ; outcome expectations were positively related to attitude toward usage ; and self-efficacy was positively related to perceived behavioral control. Thd hands-on training for the experimental group led to increases in perceived ease of use, self-efficacy and perceived behaviroal control. The changes in those variables suggest more causal effects of user training than other survey studies.

Multi-level PWM Inverter Considering the number of Output Voltage level and Current rating (출력전압 레벨 수와 전류정격을 고려한 PWM 다중레벨 인버터)

  • Park, N.S.;Seo, J.J.;Park, S.J.;Kim, K.H.;Cho, S.E.;Kim, C.U.
    • Proceedings of the KIPE Conference
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    • 2005.07a
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    • pp.659-662
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    • 2005
  • In this paper, we proposed the novel hybrid multi-level inverter using combination of the output voltage of transformers to reduce the THD(Total Harmonic Distortion) and improve the waveform of output voltage. The proposed multi-level inverter used the output of transformer which is 1times, 2times, 4times of input of the transformers. So we increased the output voltage from the reduce the number of switching component and transformer. Also, we tested the proposed prototype 15-level inverter to clarify the proposed electric circuit and reasonableness of control signal for the proposed multi -level PWM inverter.

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A New Symmetric Cascaded Multilevel Inverter Topology Using Single and Double Source Unit

  • Mohd. Ali, Jagabar Sathik;Kannan, Ramani
    • Journal of Power Electronics
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    • v.15 no.4
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    • pp.951-963
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    • 2015
  • In this paper, a new symmetric multilevel inverter is proposed. A simple structure for the cascaded multilevel inverter topology is also proposed, which produces a high number of levels with the application of few power electronic devices. The symmetric multilevel inverter can generate 2n+1 levels with a reduced number of power switches. The basic unit is composed of a single and double source unit (SDS-unit). The application of this SDS-unit is for reducing the number of power electronic components like insulated gate bipolar transistors, freewheeling diodes, gate driver circuits, dc voltage sources, and blocked voltages by switches. Various new algorithms are recommended to determine the magnitude of dc sources in a cascaded structure. Furthermore, the proposed topology is optimized for different goals. The proposed cascaded structure is compared with other similar topologies. For verifying the performance of the proposed basic symmetric and cascaded structure, results from a computer-based MATLAB/Simulink simulation and from experimental hardware are also discussed.

Analysis for forging of trochoidal gears (트로코이드 기어의 단조 해석)

  • Cho, Hae Yong;Min, Gyu Sik;Choi, Jongung
    • Journal of the Korean Society for Precision Engineering
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    • v.13 no.9
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    • pp.77-83
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    • 1996
  • This paper describes forging of trochoidal gears, which are being widely used in timing belt pulley, pump pulley etc., as a series of development of the simulator for non-axisymmetric elements. Kinematically admissible velocity fields for forging of trochoidal gear were proposed and the loads were calculated by numerical method. When the simulation was carried out, half pith of gear was divided into 6 deformation regions which have different velicity fields by assumptions and boundary conditions. The neutral surface was introduced into forging of trochoidal gears with flat punch and, for each step, it is assumed as a circle with its radius r$_{n}$. The experimental set-up was installed in 200 ton hydraulic press for forging. The billets, of A1 2218 aluminum alloy, were slightly phosphate-coated. It was shown that thd theoretical solutions, as upper bound, are useful to predict the forging load for forging of trochoidal gears, because thdt give estimates that are substantially higher than experimental loads.s.

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A COMPARATIVE STUDY ON THE FLEXURE STRENGTH OF THE CERAMICS FOR ALL-CERAMIC CROWNS (All-ceramic Crown 용 도재의 굽힘강도에 관한 비교연구)

  • Yu Hyoung-Woo;Song Chang-Yong;Bae Tae-Seong;Song Kwang-Yeob;Park Chan-Woon
    • The Journal of Korean Academy of Prosthodontics
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    • v.32 no.2
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    • pp.195-211
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    • 1994
  • The purpose of this study was to evaluate the fracture resistance of the four kinds of dental porcelains for the all-ceramic crown(Vita In-Ceram, Vita Hi-Ceram, IPS-Empress, Vitadur-N) and one kind for the metal-ceramic non(Vita VMK 68) was used as the control group. In order to determine the fracture resistance, the hi-axial flexure strength was measured at a crosshead speed of 0.5mm/min, and the Vickers hadrness was measured at an indentation load of 1kg for 20 seconds. The results obtained were summarized as follows ; 1. The maximum Weibull modulus of 24.61 for Vitadur-N and the minimum one of 852 for IPS-Empress were observed ; the maximum characteristic strength of 353.26MPa for Vita In-Ceram and the minimum that of 63.20MPa for Vitadur-N were also observed. 2. The maximum mean bi-axial flexure strength of 339.12MPa for Vita In-Ceram and thd minimum one of 61.99MPa for Vitadur-N were calculated. Results of the Scheffe test indicated that the statistically significant difference(P<0.05) existed between Vita In-Ceram or Vita Hi-Ceram and the others ; also between IPS-Empress and Vitadur-N. 3. The maximum mean hardness of $980.55kg/mm^2$ for Vita VMK 68 appeared. Results of the Scheffe test indicated that statistically significant difference(P<0.05) existed between Vita In-Ceram or Vita Hi-Ceram and the others ; also between IPS-Empress and Vita VMK 68.

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Selection of Voltage Vectors in Three-Level Five-Phase Direct Torque Control for Performance Improvement

  • Tatte, Yogesh N.;Aware, Mohan V.
    • Journal of Power Electronics
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    • v.16 no.6
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    • pp.2162-2172
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    • 2016
  • This paper presents a Direct Torque Control (DTC) strategy for the five-phase induction motor driven by a three-level five-phase inverter in order to improve the performance of the five-phase induction motor. In the proposed DTC technique, only 22 voltage vectors out of 243 available voltage vectors in a three-level five-phase inverter are selected and are divided in 10 sectors each with a width of $36^{\circ}$. The four different DTC combinations (DTC-I, II, III and IV) for a three-level five-phase induction motor drive are investigated for improving the performance of five-phase induction motor. All four of the DTC strategies utilize a combination of the same large and zero voltage vectors, but with different medium voltage vectors. Out of these four techniques, DTC-II gives the best performance when compared to the others. This DTC-II technique is analyzed in detail for improvements in the performance of five-phase induction motor in terms of torque ripple, x-y stator flux and Total Harmonics Distortion (THD) of the stator phase current when compared to its two-level counterparts. To verify the effectiveness of the proposed three-level five-phase DTC control strategy, a DSP based experimental system is build. Simulation and experimental results are provided in order to validate the proposed DTC technique.

Design Analysis and Economic Analysis of high Efficiency 100kW Generator for Hydro Power System (소수력 발전용 고효율 100kW 발전기의 설계해석 및 경제성 분석)

  • Jee, In-Ho;Kang, Seung-Jin
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.65 no.3
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    • pp.428-438
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    • 2016
  • This paper shows the design of the 100 kW IPMSG for small hydraulic power generator. The high-efficient generator, method of the dual layer interior permanent magnet was studied to improve the method of the single layer interior permanent magnet, which is mostly used. Analysis of magnet arrangement and cogging torque was done by FEM. According to structure analysis of dual layer interior permanent magnet, the amount of usage of the permanent magnet was reduced and cogging torque was decreased as well. With these successful results, the high-efficient generator design was accomplished. Based on the results of the structure analysis, the test product was designed and manufactured. And the design values and performance outputs were compared and verified with success. Also, the economic feasibility was conducted based on the electric power generated from the test product installed at the site. By the B/C analysis, in case that only SMP was analyzed, B/C ratio was 1.24 at the discount ratio of 5.5%, which considered to be economically feasible. The study is expected to be used for the application of developing large scale high-efficient interior permanent magnet synchronous generator.

A CMOS Analog Front End for a WPAN Zero-IF Receiver

  • Moon, Yeon-Kug;Seo, Hae-Moon;Park, Yong-Kuk;Won, Kwang-Ho;Lim, Seung-Ok;Kang, Jeong-Hoon;Park, Young-Choong;Yoon, Myung-Hyun;Yoo, June-Jae;Kim, Seong-Dong
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.769-772
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    • 2005
  • This paper describes a low-voltage and low-power channel selection analog front end with continuous-time low pass filters and highly linear programmable-gain amplifier(PGA). The filters were realized as balanced Gm-C biquadratic filters to achieve a low current consumption. High linearity and a constant wide bandwidth are achieved by using a new transconductance(Gm) cell. The PGA has a voltage gain varying from 0 to 65dB, while maintaining a constant bandwidth. A filter tuning circuit that requires an accurate time base but no external components is presented. With a 1-Vrms differential input and output, the filter achieves -85dB THD and a 78dB signal-to-noise ratio. Both the filter and PGA were implemented in a 0.18um 1P6M n-well CMOS process. They consume 3.2mW from a 1.8V power supply and occupy an area of $0.19mm^2$.

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원자층증착법을 이용한 Y2O3 박막 형성 및 저항 스위칭 특성

  • Jeong, Yong-Chan;Seong, Se-Jong;Lee, Myeong-Wan;Park, In-Seong;An, Jin-Ho;Rao, Venkateswara P.;Dussarrat, Christian;Noh, Wontae
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.08a
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    • pp.229.2-229.2
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    • 2013
  • Yttrium oxide (Y2O3)는 band gap이 5.5 eV 정도로 상대적으로 넓고, 굴절상수가 1.8, 유전율이 10~15, Silicon 과의 격자 불일치가 작은 특성을 가지고 있다. 또한 녹는점이 높아 열적으로 안정하기 때문에 전자소자 및 광학소자에 다양하게 응용되는 물질이다. Y2O3 박막은 다양한 방법으로 증착할 수 있는데, 그 방법에는 e-beam evaporation, laser ablation, sputtering, thermal oxidation, metal-organic chemical vapor deposition, and atomic layer deposition (ALD) 등이 있다. ALD는 기판 표면에 흡착된 원자들의 자기 제한적 반응에 의하여 박막이 증착되기 때문에 박막 두께조절이 용이하고 step coverage와 uniformity 측면에서 큰 장점이 있다. 이전에는 Y(thd)3 and Y(CH3Cp)3 와 같은 금속 전구체를 이용하여 ALD를 진행하여, 증착 속도가 낮고 defect이 많아 non-stoichiometric한 조성의 박막이 증착되는 문제점이 있었다. 이번 연구에서는, (iPrCp)2Y(iPr-amd)와 탈이온수를 사용하여 Y2O3 박막을 증착하였다. Y2O3 박막 증착에 사용한 Y 전구체는 상온에서 액체이고 $192^{\circ}C$ 에서 1 Torr의 높은 증기압을 갖는다. Y2O3 박막 증착을 위하여 Y 전구체는 $150^{\circ}C$ 로 가열하여 N2 gas를 이용하여 bubbling 방식으로 공정 챔버 내로 공급하였다. Y2O3 박막의 ALD window는 $250{\sim}350^{\circ}C$ 였으며, Y 전구체의 공급시간이 5초에 다다르자 더 이상 증착 두께가 증가하지 않는 자기 제한적 반응을 확인할 수 있었다. 그리고 증착된 Y2O3 박막의 특성 분석을 위해 Atomic force microscopy (AFM)과 X-ray photoelectron spectroscopy (XPS), Auger electron spectroscopy (AES) 를 진행하였다. 박막의 Surface morphology 는 매끄럽고 uniform 하였으며, 특히 고체 금속 전구체를 사용했을 때와 비교하여 수산화물이 거의 없는 박막을 얻을 수 있었다. 그리고 조성 분석을 통해 증착된 Y2O3 박막이 stoichiometric하다는 것을 알수 있었다. 또한 metal-insulator-metal (MIM) 구조 (Ru/Y2O3/Ru) 의 resistor 소자를 형성하여 저항 스위칭 특성을 확인하였다.

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