• 센서학회지
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• 제31권1호
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• pp.41-44
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• 2022

In this study, we have fabricated and characterized vertical double-gate (DG) InGaAs tunnel field-effect-transistors (TFETs) with Al₂O₃/HfO₂ = 1/5 nm bi-layer gate dielectric by employing a top-down approach. The device exhibited excellent characteristics including a minimum subthreshold swing of 60 mV/decade, a maximum transconductance of 141 µS/㎛, and an on/off current ratio of over 10³ at 20℃. Although the TFETs were fabricated using a dry etch-based top-down approach, the values of DIBL and hysteresis were as low as 40 mV/V and below 10 mV, respectively. By evaluating the effects of constant voltage and hot carrier injection stress on the vertical DG InGaAs TFET, we have identified the dominant charge trapping mechanism in TFETs.

• Journal of Electrical Engineering and Technology
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• 제8권6호
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• pp.1481-1486
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• 2013

In this paper, a new two dimensional (2D) analytical model of a Dual Material Gate tunnel field effect transistor (DMG TFET) is presented. The parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions. The simple and accurate analytical expressions for surface potential and electric field are derived. The electric field distribution can be used to calculate the tunneling generation rate and numerically extract tunneling current. The results show a significant improvement of on-current and reduction in short channel effects. Effectiveness of the proposed method has been confirmed by comparing the analytical results with the TCAD simulation results.

• Journal of Electrical Engineering and Technology
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• 제9권1호
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• pp.247-253
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• 2014

In this paper, a new two dimensional (2D) analytical modeling and simulation for a Dual Material Double Gate tunnel field effect transistor (DMDG TFET) is proposed. The Parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions and analytical expressions for surface potential and electric field are derived. This electric field distribution is further used to calculate the tunnelling generation rate and thus we numerically extract the tunnelling current. The results show a significant improvement in on-current characteristics while short channel effects are greatly reduced. Effectiveness of the proposed model has been confirmed by comparing the analytical results with the TCAD simulation results.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2016년도 춘계학술대회
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• pp.450-452
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• 2016

2차원 TCAD 시뮬레이션을 이용하여 L-shaped 터널링 전계효과 트랜지스터(Tunnel Field-Effect Transistor; TFET)의 도핑농도에 따른 효과를 조사했다. 소스 도핑이 $10^{20}cm^{-3}$ 이상에서 subthreshold swing (SS)이 가장 낮고, 드레인 도핑농도는 $10^{18}cm^{-3}$이하로 하는 것이 음전압에 생기는 누설전류를 막을 수 있다.

• Journal of Electrical Engineering and Technology
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• 제12권6호
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• pp.2324-2332
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• 2017

This paper presents the electrical performances of novel AlGaSb/InGaAs heterojunction-based vertical-tunneling field-effect transistor (VTFET). The device performance was investigated in views of the on-state current ($I_{on}$), drain-induced barrier thinning (DIBT), and subthreshold swing (SS) as the gate length ($L_G$) was scaled down. The proposed TFET with a $L_G$ of 5 nm operated with an $I_{on}$ of $1.3mA/{\mu}m$, a DIBT of 40 mV/V, and an SS of 23 mV/dec at a drain voltage ($V_{DS}$) of 0.23 V. The proposed TFET provided approximately 25 times lower DIBT and 12 times smaller SS compared with the conventional $L_G$ of 5 nm TFET. The AlGaSb/InGaAs VTFET showed extremely high scalability and strong immunity against short-channel effects.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권2호
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• pp.139-145
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• 2014

Control of threshold voltage ($V_T$) by ground-plane (GP) technique for planar tunnel field-effect transistor (TFET) is studied for the first time using TCAD simulation method. Although GP technique appears to be similarly useful for the TFET as for the metal-oxide-semiconductor field-effect transistor (MOSFET), some unique behaviors such as the small controllability under weak ground doping and dependence on the dopant polarity are also observed. For $V_T$-modulation larger than 100 mV, heavy ground doping over $1{\times}10^{20}cm^{-3}$ or back biasing scheme is preferred in case of TFETs. Polarity dependence is explained with a mechanism similar to the punch-through of MOSFETs. In spite of some minor differences, this result shows that both MOSFETs and TFETs can share common $V_T$-control scheme when these devices are co-integrated.

• 센서학회지
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• 제29권4호
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• pp.275-278
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• 2020

In this study, we evaluated the temperature-dependent characteristics of homojunction InGaAs vertical Fin-shaped Tunnel Field-Effect Transistors (Fin TFETs), which were fabricated using a novel nano-fin patterning technique in which the Au electroplating and the high-temperature InGaAs dry-etching processes were combined. The fabricated homojunction InGaAs vertical Fin TFETs, with a fin width and gate length of 60 nm and 100 nm, respectively, exhibited excellent device characteristics, such as a minimum subthreshold swing of 80 mV/decade for drain voltage (V_DS) = 0.3 V at 300 K. We also analyzed the temperature-dependent characteristics of the fabricated TFETs and confirmed that the on-state characteristics were insensitive to temperature variations. From 77 K to 300 K, the subthreshold swing at gate voltage (V_GS) = threshold voltage (V_T), and it was constant at 115 mV/decade, thereby indicating that the conduction mechanism through band-to-band tunneling influenced the on-state characteristics of the devices.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2018년도 추계학술대회
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• pp.381-382
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• 2018

무접합 나노선 터널 전계 효과 트렌지스터(junctionless nanowire tunnel field-effect transistor; JLNW-TFET)에서 소스(p+), 채널(i), 드레인(n) 물질으로 실리콘 및 게르마늄을 사용하여 이 구조에 대한 문턱전압 이하 기울기(subthreshold swings; SS)와 구동전류를 관찰했다. 소스-채널을 게르마늄-실리콘일 때 실리콘-실리콘, 실리콘-게르마늄, 게르마늄-게르마늄 구조보다 구동전류가 최대 1000배 증가하였고, 실리콘-실리콘 구조가 다른 구조에 비해 최소 SS가 최대 5배 이상 감소하였다.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2017년도 추계학술대회
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• pp.454-456
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• 2017

다양한 양자모델(Quantum model)을 적용한 터널 전계 효과 트랜지스터(tunnel field effect transistor; TFET)의 전류 및 커패시턴스(Capacitance)-전압 특성을 조사하였다. 사용된 양자 모델은 density gradient, Bohm Quantum Potential(BQP), Vandort quantum correction 모델을 슈뢰딩거-푸아송 모델과 calibration하여 사용하였다. BQP, Vandort, density gradient 모두 구동전류는 감소하였다. BQP를 단독으로 사용한 경우에 SS(subthreshold swing)와 on-set 전압($V_{onset}$)은 일정하지만 구동전류에서만 약 3배 전류가 감소하였으며, BQP와 Vandort 사용한 경우와 density gradient를 사용한 경우에 모두 $V_{onset}$이 약 0.07 eV 이동하였으며, SS가 40 mV/dec 이상으로 증가하였다.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2017년도 추계학술대회
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• pp.243-244
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• 2017

이 논문은 터널링 전계효과 트랜지스터의 밴드 간 터널링 전류 계산에 대하여 1차원과 2차원 방향의 터널링이 어떤 차이를 나타내는지 알아보았다. 2차원 방향의 터널링은 1차원 방향의 터널링에서 계산 되지 않는 대각선 방향의 터널링이 나타나기 때문에 더 정확한 터널링 전류를 계산할 수 있다. 시뮬레이션 결과는 문턱전압 이상의 전압에서는 2차원 방향으로 일어나는 터널링이 큰 영향을 미치지 않지만, 문턱전압 이하에서는 문턱전압 이하 기울기에 많은 영향을 미친다.