• 제목/요약/키워드: TFET

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Investigation of Trap-Assisted-Tunneling Mechanism in L-Shaped Tunneling Field-Effect-Transistor at Low Bias (L형 터널 트랜지스터의 트랩-보조-터널링 현상 조사)

  • Najam, Faraz;Yu, Yun Seop
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2019.05a
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    • pp.475-476
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    • 2019
  • L-shaped tunneling field-effect-transistor (LTFET) is considered a superior device over conventional TFETs. However, experimentally demonstrated LTFET demonstrated poor subthreshold characteristics which was attributed to trap-assisted-tunneling (TAT) caused by presence of trap states. In this paper, TAT mechanism in the experimentally demonstrated LTFET is investigated with the help of band diagram and TAT recombination rate (GTAT).

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Guide Lines for Optimal Structure of Silicon-based Pocket Tunnel Field Effect Transistor Considering Point and Line Tunneling (포인트 터널링과 라인 터널링을 모두 고려한 실리콘 기반의 포켓 터널링 전계효과 트랜지스터의 최적 구조 조건)

  • Ahn, Tae-Jun;Yu, Yun Seop
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2016.10a
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    • pp.167-169
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    • 2016
  • The structure guide lines of pocket tunnel field effect transistor(TFET) considering Line and Point tunneling are introduced. As the pocket doping concentration or thickness increase, on-current $I_{on}$ increases. As the pocket thickness or gate insulator increase, subthreshold swing(SS) increases. Optimal structure reducing the hump effects should be proposed in order to enhance SS.

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Optimization of Tunneling FET with Suppression of Leakage Current and Improvement of Subthreshold Slope (누설전류 감소 및 Subthreshold Slope 향상을 위한 Tunneling FET 소자 최적화)

  • Yoon, Hyun-kyung;Lee, Jae-hoon;Lee, Ho-seong;Park, Jong-tae
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2013.10a
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    • pp.713-716
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    • 2013
  • The device performances of N-channel Tunneling FET have been characterized with different intrinsic length between drain and gate($L_{in}$), drain and source doping, permittivity and oxide thickness when the total effective channel length is constant. N-channel Tunneling FET of SOI structure have been used in characterization. $L_{in}$ was from 30nm to 70nm, dose concentration of drain and source were from $2{\times}10^{12}cm^{-2}$ to $2{\times}10^{15}cm^{-2}$ and from $1{\times}10^{14}cm^{-2}$ to $3{\times}10^{15}cm^{-2}$, permittivity was from 3.9 to 29, and oxide thickness was from 3nm to 9nm. The device performances were characterized by Subthreshold slope(S-slope), On/off ratio, and leakage current. From the simulation results, the leakage current have been reduced for long $L_{in}$ and low drain doping. S-slope have been reduced for high source doping, high permittivity and thin oxide thickness. With considering the leakage current and S-slope, it is desirable that are long $L_{in}$, low drain doping, high source doping, high permittivity and thin oxide thickness to optimize device performance in n-channel Tunneling FET.

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