• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.2
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• pp.117-123
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• 2004

A 30 nm $In_{0.7}GaAs$ High Electron Mobility Transistor (HEMT) with triple-gate has been successfully fabricated using the $SiO_2/SiN_x$ sidewall process and BCB planarization. The sidewall gate process was used to obtain finer lines, and the width of the initial line could be lessened to half by this process. To fill the Schottky metal effectively to a narrow gate line after applying the developed sidewall process, the sputtered tungsten (W) metal was utilized instead of conventional e-beam evaporated metal. To reduce the parasitic capacitance through dielectric layers and the gate metal resistance ($R_g$), the etchedback BCB with a low dielectric constant was used as the supporting layer of a wide gate head, which also offered extremely low Rg of 1.7 Ohm for a total gate width ($W_g$) of 2x100m. The fabricated 30nm $In_{0.7}GaAs$ HEMTs showed $V_{th}$of -0.4V, $G_{m,max}$ of 1.7S/mm, and $f_T$ of 421GHz. These results indicate that InGaAs nano-HEMT with excellent device performance could be successfully fabricated through a reproducible and damage-free sidewall process without the aid of state-of-the-art lithography equipment. We also believe that the developed process will be directly applicable to the fabrication of deep sub-50nm InGaAs HEMTs if the initial line length can be reduced to below 50nm order.

• Journal of Electrical Engineering and Technology
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• v.1 no.2
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• pp.237-240
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• 2006

The feasibility of a midgap metal gate is investigated for a 32 nm MOSFET for low power applications. The midgap metal gate MOSFET is found to deliver $I_{on}$ as high as a bandedge gate if a proper retrograde channel is used. An adequate design of the retrograde channel is essential to achieve the performance requirement given in the ITRS roadmap. A process simulation is also run to evaluate the feasibility of the necessary retrograde profile in manufacturing environments. Based on the simulated result, it is found that any subsequent thermal process should be tightly controlled to retain transistor performance, which is achieved using the retrograde doping profile. Also, the bandedge gate MOSFET is determined be more vulnerable to the subsequent thermal processes than the midgap gate MOSFET. A guideline for gate workfunction $(\Phi_m)$ is suggested for the 32 nm MOSFET.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.2
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• pp.244-250
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• 1994

This paper presents the design of a new turn-off gate drive circuit for GTO which can accomplish faster turn-off switching. The major disadvantage of the conventional turn-off gate drive technique is that it has a difficulty in realizing high negative diS1GQT/dt because of VS1RGM(maximum reverse gate voltage) and stray inductances of turn-off gate drive circuit[1~2]. The new trun-off gate drive technique can overcome this problem by adding another turn-off gate drive circuit to the conventional turn-off gate drive circuit. Simulation and experimental results of the new turn-off gate drive circuit in conjunction with chopper circuit verify a faster turn-off switching performance.

• Journal of Ocean Engineering and Technology
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• v.5 no.1
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• pp.64-70
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• 1991

The design theory of roller gate has been systematized laying more emphasis on practical formulas than theoretical ones and the design procedure of the existing gate facilites is reviewed and analyaed on economical viewpoint and safety factor. The design theory of timoshenko, the thechnical standards for hydraulic gate and penstock of Japan, and the design standards for waterworks structures of Germany are applied to the study of optimal design of a gate leaf. In this study, gate leaf which is now being operated for water control at the seadike, estuary dam and reservoir dam are adopted as a mode, and a new design method by the computer is proposed through the variation of design elements within practical ranges. As a result, safety factor and economical design can be made by using T-beams to the horizontal and vertical beam of the gate leaf instead of H-beams used in the existing seadike roller gate at Asan, and total weight of gate leaf is reduced by the present optimization.

• Journal of Electrical Engineering and information Science
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• v.2 no.3
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• pp.132-138
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• 1997

Electrical characteristics of split-gate flash EEPROM with triple polysilicon is investigated in terms of effects of floating gate and offset gate. In order to search for t the effects of offset gate on programming characteristics, threshold voltage and drain current are studied with variation of control gate voltage. The programming process is believed to depend on vertical and horizontal electric field as well as offset gate length. The erase and program threshold voltage are found to be almost constant with variation of control gate voltage above 12V, while endurance test indicates degradation of program threshold voltage. With increase of offset gate length, program threshold voltage becomes smaller and the drain source voltage just after program under constant control gate voltage becomes higher.

• ETRI Journal
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• v.18 no.3
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• pp.171-179
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• 1996

Fully passivated low noise AlGaAs/InGaAs/GaAs pseudomorphic (PM) HEMT with wide head T-shaped gates were fabricated by dose split electron beam lithography (DSL). The dimensions of gate head and footprint were optimized by controlling the splitted pattern size, dose, and spaces of each pattern. We obtained stable T-shaped gate of $0.15{\mu}m$ gate length with $1.35{\mu}m-wide$ head. The maximum extrinsic transconductance was 560 mS/mm. The minimum noise figure measured at 18 GHz at $V_{ds}=2V andI_{ds}=17mA$ was 0.41 dB with associated gain of 8.19 dB. At 12 GHz, the minimum noise figure and an associated gain were 0.26 and 10.25 dB, respectively. These noise figures are the lowest values ever reported for GaAs-based HEMTs. These results are attributed to the extremely low gate resistance of wide head T-shaped gate having a ratio of the head to footprint dimensions larger than 9.

• The Journal of the Convergence on Culture Technology
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• v.7 no.1
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• pp.558-563
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• 2021

Quantum-Dot Cellular Automata is a next-generation nanocircular design technology that is drawing attention from many research organizations not only because it is possible to design efficient circuits by overcoming the physical size limitations of existing CMOS circuits, but also because of its energy-efficient features. In this paper, one of the existing digital circuits, T flip-flop circuit, is proposed using QCA. The previously proposed T flip-flops are designed based on the majority gate, so the circuits are complex and have long delays. Therefore, the design of the XOR gate-based T flip-flop using cell interaction reduces circuit complexity and minimizes latency. The proposed circuit is simulated using QCADesigner, and the performance is compared and analyzed with the existing proposed circuits.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.2
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• pp.63-66
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• 2017

This research was about shielded trench gate power MOSFET for low voltage and high speed. We used T-CAD tool and carried out process and device simulation for exracting design and process parameters. The exracted parameters was used to design shieled and conventional trench gate power MOSFET. And The electrical characteristics of shieled and conventional trench gate power MOSFET were compared and analyzed for their power device applications. As a result of analyzing electrical characteristics, the recorded breakdown voltages of both devices were around 120 V. The electric distributions of shielded and conventional trench gate power MOSFET was different. But due to the low voltage level, the breakdown voltage was almost same. And the other hand, the threshold voltage characteristics of shielded trench gate power MOSFET was superior to convention trench gate power MOSFET. In terms of on resistance characteristics, we obtained optimal oxied thickness of $3{\mu}m$.

• Journal of the Korean Magnetics Society
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• v.22 no.2
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• pp.45-48
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• 2012

Feed-back type 3-axis flux-gate magnetometer using Co-based amorphous ribbon (Metglass$^{(R)}$2714A) was constructed in this work. Measuring range of magnetic field and frequency were ${\pm}100\;{\mu}T$ and dc~10 Hz respectively. For the interface to computer, microcontroller and 24 bit ADC (Analog to Digital Converter) were employed and resolution of digital output was 0.1 nT. Magnetometer noise of analog output was 5 pT/$\sqrt{Hz}$ at 1 Hz. Digital output of the magnetometer showed linearity of $1{\times}10^{-4}$ and the offset drift was smaller than 0.2 nT during 1 h.

• Journal of Advanced Navigation Technology
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• v.23 no.2
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• pp.207-213
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• 2019

Recently, the importance for internet of things (IoT) security has increased enormously and hardware-based compact chips are needed in IoT communication industries. In this paper, we propose low-complexity crypto-processor that unifies advanced encryption standard (AES), academy, research, institute, agency (ARIA), and CLEFIA protocols into one combined design. In the proposed crypto-processor, encryption and decryption processes are shared, and 128-bit round key generation process is combined. Moreover, the shared design has been minimized to be adapted in generic IoT devices and systems including lightweight IoT devices. The proposed crypto-processor was implemented in Verilog hardware description language (HDL) and synthesized to gate level circuit in 65nm CMOS process, which results in 11,080 gate counts. This demonstrates roughly 42% better than the aggregates of three algorithm implementations in the aspect of gate counts.