• Nuclear Engineering and Technology
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• v.41 no.1
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• pp.79-90
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• 2009

Verification of programmable logic controller (PLC) programs written in IEC 61131-3 function block diagram (FBD) is essential in the transition from the use of traditional relay-based analog systems to PLC-based digital systems. This paper describes effective use of the well-known verification tool VIS for automatic verification of behavioral equivalences between successive FBD revisions. We formally defined FBD semantics as a state-transition system, developed semantic-preserving translation rules from FBD to Verilog programs, implemented a software tool to support the process, and conducted a case study on a subset of FBDs for APR-1400 reactor protection system design.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.12
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• pp.2286-2292
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• 2008

In this paper, we design a RS(23,17) decoder for MB-OFDM(Multiband-Orthogonal Frequency Division Multiplexing) system, in which Modified Euclidean(ME) algorithm is adopted for key equation solver block. The proposed decoder has been optimized for MB-OFDM system so that it has less latency and hardware complexity. Additionally, we have implemented the proposed decoder using Verilog HDL and synthesized with Samsung 65nm library. From synthesis results, it can operate at clock frequency of 250MHz, and gate count is 20,710.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.67 no.1
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• pp.9-14
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• 2018

In this paper, we introduce an AES-based security chip for the embedded system of Internet of Things(IoT). We used Verilog HDL to implement the AES algorithm in FPGA. The designed AES module creates 128-bit cipher by encrypting 128-bit plain text and vice versa. RTL simulations are performed to verify the AES function and the theory is compared to the results. An FPGA emulation was also performed with 40 types of test sequences using two Altera DE0-Nano-SoC boards. To evaluate the performance of security algorithms, we compared them with AES implemented by software. The processing cycle per data unit of hardware implementation is 3.9 to 7.7 times faster than software implementation. However, there is a possibility that the processing speed grow slower due to the feature of the hardware design. This can be solved by using a pipelined scheme that divides the propagation delay time or by using an ASIC design method. In addition to the AES algorithm designed in this paper, various algorithms such as IPSec can be implemented in hardware. If hardware IP design is set in advance, future IoT applications will be able to improve security strength without time difficulties.

• Journal of IKEEE
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• v.25 no.1
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• pp.10-14
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• 2021

This paper presents a hardware that improves the complexity of the CIE1931 color coordinate algorithm operation. The conventional algorithm has disadvantage of growing hardware due to 4-Split Multiply operations used to calculate large bits in the computation process. But the proposed algorithm pre-calculates the defined R2X, X2R Matrix operations of the conventional algorithm and makes them a matrix. By applying the matrix to the images and improving the color, it is possible to reduce the amount of computation and hardware size. By comparing the results of Xilinx synthesis of hardware designed with Verilog, we can check the performance for real-time processing in 4K environments with reduced hardware resources. Furthermore, this paper validates the hardware mount behavior by presenting the execution results of the FPGA board.

• Journal of Korea Multimedia Society
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• v.1 no.2
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• pp.154-161
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• 1998

This paper proposes a parallel processor system which processes cultural assets image recognition and retrieval algorithm in real time. A serial algorithm which is developed for the parallel processor system is parallellized. The parallel processor system consists of a control unit, 100 PE(Processing Elements), and 10 Park's multi-access memory systems which has 11 memory modules per each one. The parallel processor system is simulated by CADENCE Verilog-XL which is a package for the hardware simulation. With the same simulated results as that of the serial algorithm, the speed ratio of the parallel algorithm to the serial one is 81. The parallel processor system we proposed is quite effective for cultural assets image processing.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.10
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• pp.1537-1544
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• 2022

When designing chip, it considers design specification, timing problem, and clock synchronization on place & route (P&R) process. P&R process is complicated because of considering various factors. Chip uses clock tree synthesis (CTS) to reduce clock path delay. The purpose of this study is to examine shallow-CTS algorithm for checking clock tree synthesizable. Using open source Parser-Verilog, register transfer level (RTL) synthesizable Verilog file is parsed and it uses Pre-CTS and Post-CTS process that is included shallow-CTS. Based on longest clock path in the Pre-CTS and Post-CTS stages, the standard deviation before and after buffer insertion is compared and analyzed for the accuracy of CTS. In this paper, It is expected that the cost and time problem could be reduced by providing a pre-clock tree synthesis verification method at the RTL level without confirming the CTS result using the time-consuming licensed EDA tool.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2021.05a
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• pp.600-602
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• 2021

With the development of the mobile industry and growing interest in artificial intelligence (AI) technology, a lot of research for AI processors which applicable to embedded systems is under study. When implementing AI to embedded systems, the design should be considered the restriction of resource and power consumption. Moreover, it is efficient to include a dedicated hardware accelerator in order to complement the low computational performance of the embedded system. In this paper, we propose an stand-alone embedded AI processor. The proposed AI processor includes a hardware accelerator that is dedicated to the distance-based AI algorithm and a general-purpose MCU that supports flexible programmability for application to various embedded systems. The AI processor was designed with Verilog HDL and verified by implementing on Field Programmable Gate Array (FPGA).

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.2
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• pp.177-182
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• 2010

The flow of a universal system-level design methodology consists of system specification, system-level hardware/software partitioning, co-design, co-verification using virtual or physical prototype, and system integration. In the developing process of a hardware component in system, the design phase has been regarded as a phase consuming lots of time and cost. However, the verification phase in which functionality of the designed component is verified has recently been considered as a much important phase. In this paper, the implementation of a verification environment which is based on SystemC infrastructure and verifies the functionality of a hardware component is described. The proposed verification system uses SystemC user-defined channel as communication interface between variables of SystemC module and registers of Verilog module. The functional verification of an UART is performed on the proposed verification system. SystemC provides class library for hardware modeling and has an advantage of being able to design a system consisting hardware and software in higher abstraction level than register transfer level. Source codes of SystemC modules are reusable with a minor adaptation on verifying functionality of another hardware component.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.6
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• pp.83-89
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• 2012

This paper proposes the design of a security-enhanced RFID authentication protocol which meets the privacy protection for tag bearers. The protocol which uses AES(Advanced Encryption Standard) cipher algorithm is based on a three-way challenge response authentication scheme. In addition, three different types of protocol packet formats are also presented by extending the ISO/IEC 18000-3 standard for realizing the security-enhanced authentication mechanism in RFID system environment. Through the comparison of security, it was shown that the proposed scheme has better performance in user data confidentiality, Man-in-the-middle replay attack, and replay attack, and forgery resistance, compared with conventional some protocols. In order to validate the proposed protocol, a digital Codec of RFID tag is also designed based on the protocol. This Codec has been described in Verilog HDL and also synthesized using Xilinx Virtex XCV400E device.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.585-588
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• 2004

This paper describes design and verification of the motion estimation and compensation unit using full search algorithm. Video processor is the key device of video communication systems. Motion estimation is the key module of video processor. The technologies of motion estimation and compensation unit are the core technologies for wireless video telecommunications system, portable multimedia systems. In this design, Verilog simulator and logic synthesis tools are used for hardware design and verification. In this paper, motion estimation and compensation unit are designed using FPGA, coded in Verilog HDL, and simulated and verified using Xilinx FPGA.