• Title/Summary/Keyword: System-on-Chip

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A Study on the Charactistics of Machined Surface due to Cutter Runout (커터 런 아웃과 가공표면 생성에 관한 연구)

  • Hwang, J.;Lee, K. Y.;Shin, S. C.;Chung, E. S.
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 1997.04a
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    • pp.873-877
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    • 1997
  • This paper presents experimental results to know the charcteristics of machined surface due to cutter runout. Cutter runout is a common but undesirable phenomenon in multi-tooth machining such as end-milling process because it introduces variable chip loading to insert which results in a accelerated tool wear, amplification of force variation and hence enargement vibration amplitude. To develop in-proess cutter runout compensation system, set-up the micro-positoning mechanism which is based on piezoelectric translator embeded in the work holder to manipulate the depth of cut in real-time. And feasibility test of system was done under the various experimental cutting conditions. This results provide lots of information to build-up the precision machining technology.

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A Real-Time Operating System for System-on-Chip Design and Verification (SoC(System-on-Chip) 설계와 검증을 지원하는 실시간운영체제)

  • Kim, Ji-Min;Ryu, Min-Soo
    • Annual Conference of KIPS
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    • 2005.05a
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    • pp.1679-1682
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    • 2005
  • 최근 SoC를 포함하는 대부분의 임베디드시스템에서는 RTOS가 선택이 아닌 필수적인 구성요소가 됨에 따라 SoC 개발의 초기단계에서부터 RTOS를 도입하는 것이 바람직하다. 하지만, 기존의 범용 RTOS가 제공하는 기능은 대부분 응용 소프트웨어의 개발과 수행을 위한 것으로 SoC 개발 및 검증에는 적합하지 않은 문제점을 가지고 있다. 본 연구에서는 SoC 개발을 위해 운영체제가 만족시켜야할 요구사항을 제시하고, 소프트웨어의 재사용성과 SoC의 검증을 함께 지원하는 VPOS(Verification-Purpose OS)를 개발하였다. VPOS는 초경량의 단순한 계층적 구조(layered structure)를 가지는 RTOS로서 소프트웨어 재사용을 위해 POSIX 표준 API, 유닉스 호환 디바이스 드라이버 인터페이스, HAL 등을 제공한다. 또한 SoC 설계의 검증을 위해 RT 수준의 통합시뮬레이션에 적합한 커널 구조 및 최적화된 코드, 하드웨어 테스트를 위한 쉘 명령어, 응용 소프트웨어의 디버깅을 위한 KREM(kernel resource and event monitoring) 등의 특징을 함께 제공한다.

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Modeling and Simulation for Level & Flow Control System Using Microcontroller

  • Unhavanich, Sumalee;Dumawipata, Teerasilapa;Tangsrirat, Worapong
    • 제어로봇시스템학회:학술대회논문집
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    • 2001.10a
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    • pp.86.5-86
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    • 2001
  • This work describes a design and implementation of the level & flow rate control system by using a single-chip microcontroller. The proposed model system is designed based on the use of the single-chip microcontroller 8031 with the EPROM emulator for programming the computer software. The microcontroller reaches the input level and flow signals from the level sensor and the turbine flowmeter, respectively, via the signal conditioning circuits and A/D converters in order to calculate the control signal. Moreover, the status of the process variable can easily be set up and controlled by program monitoring through the emulator, and can be graphically displayed on the computer screen. Experiment results were carried out which can be ...

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A Continuous Electrical Cell Lysis Chip using a DC Bias Voltage for Cell Disruption and Electroosmotic Flow (한 쌍의 전극으로 전기 삼투 유동과 세포 분쇄 기능을 동시에 구현한 연속적인 세포 분쇄기)

  • Lee, Dong-Woo;Cho, Young-Ho
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.32 no.10
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    • pp.831-835
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    • 2008
  • We present a continuous electrical cell lysis chip, using a DC bias voltage to generate the focused high electric field for cell lysis as well as the electroosmotic flow for cell transport. The previous cell lysis chips apply an AC voltage between micro-gap electrodes for cell lysis and use pumps or valves for cell transport. The present DC chip generates high electrical field by reducing the width of the channel between a DC electrode pair, while the previous AC chips reducing the gap between an AC electrode pair. The present chip performs continuous cell pumping without using additional flow source, while the previous chips need additional pumps or valves for the discontinuous cell loading and unloading in the lysis chambers. The experimental study features an orifice whose width and length is 20 times narrower and 175 times shorter than the width and length of a microchannel. With an operational voltage of 50 V, the present chip generates high electric field strength of 1.2 kV/cm at the orifice to disrupt cells with 100% lysis rate of Red Blood Cells and low electric field strength of 60 V/cm at the microchannel to generate an electroosmotic flow of $30{\mu}m/s{\pm}9{\mu}m/s$. In conclusion, the present chip is capable of continuous self-pumping cell lysis at a low voltage; thus, it is suitable for a sample pretreatment component of a micro total analysis system or lab-on-a-chip.

A Study on the MHD Micropump with Mixing Function (혼합 기능을 갖는 마이크로 펌프의 연구)

  • Choi, Bum-Kyoo;Kang, Ho-Jin;Kim, Min-Sock
    • Transactions of the Korean Society of Mechanical Engineers B
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    • v.34 no.6
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    • pp.579-586
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    • 2010
  • With the development of micrototal analysis systems (${\mu}TAS$), which is a result of enhancement of MEMS technology, rapid progress has been achieved in medical and biological research. The study of lab-on-a-chip (LOC) devices, which are types of ${\mu}TAS$ and which integrate the functions of mixing and analyzing tiny amounts of samples and reagents on one chip, has actively progressed. An LOC comprises microfluidic components such as micromixers and micropumps. Because the flow in a microfluidic system is generally laminar, it is very difficult to efficiently mix and feed fluid reagents. This paper presents the design and the method of fabrication of an MHD micropump for mixing fluids. By using this micropump, fluids are simultaneously mixed and pumped; this is achieved by coupling the Lorentz force and force exerted by an electric charge moving in an electric field.

Run-Time Hardware Trojans Detection Using On-Chip Bus for System-on-Chip Design (온칩버스를 이용한 런타임 하드웨어 트로이 목마 검출 SoC 설계)

  • Kanda, Guard;Park, Seungyong;Ryoo, Kwangki
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.2
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    • pp.343-350
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    • 2016
  • A secure and effective on-chip bus for detecting and preventing malicious attacks by infected IPs is presented in this paper. Most system inter-connects (on-chip bus) are vulnerable to hardware Trojan (Malware) attack because all data and control signals are routed. A proposed secure bus with modifications in arbitration, address decoding, and wrapping for bus master and slaves is designed using the Advanced High-Performance and Advance Peripheral Bus (AHB and APB Bus). It is implemented with the concept that arbiter checks share of masters and manage infected masters and slaves in every transaction. The proposed hardware is designed with the Xilinx 14.7 ISE and verified using the HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA device. The design has a total gate count of 39K at an operating frequency of 313MHz using the $0.13{\mu}m$ TSMC process.

Numerical Simulation of Heat Transfer in Chip-in-Board Package (Chip-in-Board 패키지의 열전달 해석)

  • Park, Joon Hyoung;Shim, Hee Soo;Kim, Sun Kyoung
    • Transactions of the Korean Society of Mechanical Engineers B
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    • v.37 no.1
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    • pp.75-79
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    • 2013
  • Demands for semiconductor devices are dramatically increasing, and advancements in fabrication technology are allowing a step-up in the number of devices per unit area. As a result, semiconductor devices require higher heat dissipation, and thus, cooling solutions have become important for guaranteeing their operational reliability. In particular, in chip-in-board packages, in which chips and passives are embedded in the substrates for efficient device layout, heat dissipation is of greater importance. In this study, a thermal model for layers of different materials has been proposed, and then, the heat transfer has been simulated by imposing a set of appropriate boundary conditions. Heat generation can be predicted based on the results, which will be utilized as practical data for actual package design.

Similarity Evaluation and Analysis of Source Code Materials for SOC System in IoT Devices (사물인터넷 디바이스의 집적회로 목적물과 소스코드의 유사성 분석 및 동일성)

  • Kim, Do-Hyeun;Lee, Kyu-Tae
    • Journal of Software Assessment and Valuation
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    • v.15 no.1
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    • pp.55-62
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    • 2019
  • The needs for small size and low power consumption of information devices is being implemented with SOC technology that implements the program on a single chip in Internet of Thing. Copyright disputes due to piracy are increasing in semiconductor chips as well, arising from disputes in the chip implementation of the design house and chip implementation by the illegal use of the source code. However, since the final chip implementation is made in the design house, it is difficult to protect the copyright. In this paper, we deal with the analysis method for extracting similarity and the criteria for setting similarity judgment in the dispute of source code written in HDL language. Especially, the chip which is manufactured based on the same specification will be divided into the same configuration and the code type.

Automated Protein-Expression Profiling System using Crude Protein Direct Blotting Method

  • Kobayashi, Hironori;Torikoshi, Yasuhiro;Kawasaki, Yuko;Ishihara, Hideki;Mizumoto, Hiroshi
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.2356-2361
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    • 2003
  • Proteome research in the medical field is expected to accelerate the understanding of disease mechanism, and to create new diagnostic concept. For protein profiling, this paper proposes a new methodology named CPDIB (Crude Protein Direct Blotting). In the CPDIB procedure, crude protein sample is directly immobilized on a membrane and the expression of protein molecules in the sample are analyzed quantitatively by using a special device called ImmobiChip, where the membrane is used as a field of the immune reaction. The over-all structure of the ImmobiChip is based on the conventional Slot blot device. Mechanical improvement in the air-tightness of the case holding the membrane realizes the direct blotting and results in high performance of stability in the immune reaction. In the measurement of multiple proteins, a dispensing robot is used for increasing the efficiency of handling of liquid. Cooperation of the dispensing robot with the ImmobiChip for immobilizing proteins realizes automated and stable performance of the CPDIB procedure. This paper shows the evaluation of the air-tightness of the ImmobiChip, the ability of analyzing proteins using the CPDIB procedure and the performance of the automated equipment.

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ARM Professor-based programmable BIST for Embedded Memory in SoC (SoC 내장 메모리를 위한 ARM 프로세서 기반의 프로그래머블 BIST)

  • Lee, Min-Ho;Hong, Won-Gi;Song, Jwa-Hee;Chang, Hoon
    • Journal of KIISE:Computer Systems and Theory
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    • v.35 no.6
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    • pp.284-292
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    • 2008
  • The density of Memory has been increased by great challenge for memory technology; therefore, elements of memory become more smaller than before and the sensitivity to faults increases. As a result of these changes, memory testing becomes more complex. In addition, as the number of storage elements per chip increases, the test cost becomes more remarkable as the cost per transistor drops. Recent development in system-on-chip(SoC) technology makes it possible to incorporate large embedded memories into a chip. However, it also complicates the test process, since usually the embedded memories cannot be controlled from the external environment. We present a ARM processor-programmable built-in self-test(BIST) scheme suitable for embedded memory testing in the SoC environment. The proposed BIST circuit can be programmed vis an on-chip microprocessor.