• Journal of Sensor Science and Technology
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• v.28 no.4
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• pp.221-224
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• 2019

Based on the results of studies on acetone excretion in diabetic patients, a one - chip sensors array was fabricated by combining acetone-selective sensor materials and volatile-organic-compound sensitive sensor materials. An electonic-nose was implemented using a sensor array and confirmed selectivity for five gases. In this system, the excretion of diabetic patients and controls was sampled with solid phase microextraction fiber and transferred to the sensor array. Although the control and diabetic patients were distinct, several samples failed. In the control group, the results of blood tests were normal, but patients were highly obese. In addition, the gas chromatography mass spectrometry results for the subjects revealed chemicals that are external factors.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.8
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• pp.1899-1907
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• 2013

This paper presents an efficient defect detection and classification system based on reference image for COF (Chip-on-Film) which encounters fatal defects after ultra fine pattern fabrication. These defects include typical ones such as open, mouse bite (near open), hard short and soft short. In order to detect these defects, conventionally it needs visual examination or electric circuits. However, these methods requires huge amount of time and money. In this paper, based on reference image, the proposed system detects fatal defect and efficiently classifies it to one of 4 types. The proposed system includes the preprocessing of the test image, the extraction of ROI, the analysis of local binary pattern and classification. Through simulations with lots of sample images, it is shown that the proposed system is very efficient in reducing huge amount of time and money for detecting the defects of ultra fine pattern COF.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.449-450
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• 2008

In this paper, we present the design of a system on a chip(SoC) based on Powerline Communication for Power-IT. The SoC deals with power information obtained from analog to digital converter and transmits this data via powerline. We integrate main processor, ADC and PLC function into a chip. Also a FPGA-based emulation system is introduced to evaluate a proposed SoC architecture.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.736-744
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• 2016

Network on chip (NoC) is an emerging technology in the field of multi core interconnection architecture. The routers plays an essential components of Network on chip and responsible for packet delivery by selecting shortest path between source and destination. State-of-the-art NoC designs used routing table to find the shortest path and supports four ports for packet transfer, which consume high power consumption and degrades the system performance. In this paper, the multi port multi core router architecture is proposed to reduce the power consumption and increasing the throughput of the system. The shared buffer is employed between the multi ports of the router architecture. The performance of the proposed router is analyzed in terms of power and current consumption with conventional methods. The proposed system uses Modelsim software for simulation purposes and Xilinx Project Navigator for synthesis purposes. The proposed architecture consumes 31 mW on CPLD XC2C64A processor.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.212-215
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• 2005

The needs of larger screen in mobile device would be increased as the time of ubiquitous and convergence is coming. And, the type of mobile device has been evolved from bar, slide to row. Recently, the study on the multi-display screen which has seamless gap between two display panel has been published, and moreover the System On Chip(SOC) design strategy of core chip has been the most promising Field-Programmable Gate Array(FPGA) technology in the display system. Therefore, in this paper, we proposed the design technique of SOC and evaluated the effectiveness with Very high speed Hardware Description Language(VHDL) Intellectual Property (IP) for the operation of multi display device driver. Also, This IP design would be to allow any kind of user interface in control system.

• Journal of Life Science
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• v.13 no.1
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• pp.99-104
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• 2003

Aromatic compounds are of major concern among environmental pollutants due to their toxicity and persistence. To monitor aromatic compounds in a real time with a better sensitivity, a new method of SPR (surface plasmon resonance) based on DNA chip (Biacore 3000) was developed here. It is thought that CapR regulatory protein as a complex with phenol, could bind to their corresponding promoter, Po. Biotinylated DNA oligomers for the promoter was synthesized by PCR and coupled onto streptoavidin-linked CM5-chip. CapR regulatory proteins were purified after cloning their genes in pET21a (+) vector and expressing proteins. The interaction was assessed by the system where the regulatory proteins flowed with or without phenol through the cells of DNA chip. CapR regulatory protein even in the presence of phenol had no response to its promoter, Po, suggesting that other factor(s) might be required for the activation of Po promoter. The present work reveals a promising possibility of the SPR-based DNA chip in monitoring specific environmental pollutants in a real time.

• 한국전산유체공학회:학술대회논문집
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• 2011.05a
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• pp.117-123
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• 2011

The low electric power and high efficiency chips are required because of the appearance of smart phones. Also, high-capacity memory chips are needed. e-MMC(embedded Multi-Media Card) for this is defined by JEDEC(Joint Electron Device Engineering Council). The e-MMC memory for research and development is a memory mulit-chip module of 64GB using 16-multilayers of 4GB NAND-flash memory. And it has simplified the chip by using SIP technique. But mulit-chip module generates high heat by higher integration. According to the result of study, whenever semiconductor chip is about 10 $^{\circ}C$ higher than the design temperature it makes the life of the chip shorten more than 50%. Therefore, it is required that we solve the problem of heating value and make the efficiency of e-MMC improved. In this study, geometry of 16-multilayered structure is compared the temperature distribution of four different geometries along the numerical analysis. As a result, it is con finned that a multilayer structure of stair type is more efficient than a multilayer structure of vertical type because a multi-layer structure of stair type is about 9 $^{\circ}C$ lower than a multilayer structure of vertical type.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7A
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• pp.635-640
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• 2002

We investigate optimal and suboptimal decision rules for parallel code acquisition in chip asynchronous direct-sequence spread-spectrum systems. The conventional decision rule for parallel acquisition is to choose the largest correlator output of a receiver. However, such a scheme is optimum only for chip synchronous models. In this paper, an optimal decision rule is derived based on the maximum-likehood criterion for chip asynchronous models. A simpler suboptimal decision rule is also discussed. The performance of the optimum and suboptimum decision rules is compared to that of the conventional decision rule. Numerical results show that, for chip asynchronous models, both the optimal and suboptimal decision rules outperform the conventional decision rule.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.9
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• pp.4138-4146
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• 2011

In surface mount technology, with cellular phones and flat panel displays shrinking in size, the electric goods for making these things are getting smaller as well. Therefore, the technology of mounting components such as 0402 and 0603 Chip is on the rise. The chip mount manufacturing companies have studied the mount technology to prevent the missing insertions or improper insertion. This study suggests arranging the mechanical structure by using fiber sensors to eliminate missing insertions or improper insertions and developing the technology for upgrading system algorithms.

• International Journal of Precision Engineering and Manufacturing
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• v.2 no.2
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• pp.38-47
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• 2001

This paper decribes the development of computer-aided design of a very precise progressice die for lead frame of semiconductor chip. The approach to the system is based on knowledgr-based rules. Knowledge of fie이 experts. This system has been written in AutoLISP using AutoCAD ona personal computer and the I-DEAS drafting programming Language on the I-DEAS mater series drafting with on HP9000/715(64) workstation. Data exchange between AutoCAD and I-DEAS master series drafting is accomplished using DXF(drawing exchange format) and IGES(initial graphics exchange specification) files. This system is composed of six main modules, which are input and shape treatment, production feasibility check, strip layout, data conversion, die layout, and post processing modules. Based on Knowledge-based rules, the system considers several factors, such as V-notches, dimple, pad chamfer, spank, cavity punch, camber, coined area, cross bow, material and thickness of product, complexities of blank geometry and punch profiles, specifications of available presses, and the availability of standard parts. As forming processes and the die design system using 2D geometry recognition are integrated with the technology of process planning, die design, and CAE analysis, the standardization of die part for lead frames requiting a high precision process is possible. The die layout drawing generated by the die layout module s displayed in graphic form. The developed system makes it possible to design and manufacture lead frame of a semiconductor more efficiently.