• Journal of Korean Society of Industrial and Systems Engineering
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• v.25 no.2
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• pp.11-18
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• 2002

Psychological and physiological effects of the simulator sickness could be important bias factors for the sensibility evaluation. The purpose of the present study was to clear the differences of psychophysiological responses due to individual sensitivity of simulator sickness. The present experiment tried to investigate the simulator sickness objectively by observing the change of the simulator sickness for the different level of sickness groups (sick and non_sick group). The subjective evaluations using Simulator Sickness Questionnaire (SSQ) and physiological responses were measured every five minutes when they were driving as 60km/h in the driving graphic simulator. Response level of the subjective evaluation for all subjects on the simulator sickness was linearly increased with time for every item, and the response level of sick group was bigger than that of non_sick group. When the analysis on central nervous system was done separately on the sick and the non_sick group, there was significant difference in the parameter $\theta$/total at Fz and Cz. Although the analysis on autonomic nervous system for all subjects showed the increased activation of sympathetic nervous system, there was no significant difference between the sick and non_sick group. In summary, it is necessary to select the subjects who feel less simulator sickness in order to be accurate sensibility evaluation. The parameters to distinguish between the sick and non_sick group were the change on $\theta$/total and subjective evaluation using SSQ.

• Science of Emotion and Sensibility
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• v.4 no.1
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• pp.23-31
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• 2001

Psychological and physiological effects from simulator sickness could be an important bias factor for sensibility evaluation. The present experiment investigated the effects of simulator sickness on sensibility evaluation in the controlled condition of driving a car for 60 minutes on a constant speed (60km/h) in graphic simulator. The simulator sickness was measured and analysed for every five minutes using their subjective evaluation and physiological signals. Results of the subjective evaluation showed that there was significant difference between rest and driving condition at 10 minutes from the start of driving, and the level of difference was increased linearly with time. The analysis on central and autonomic nervous systems showed the significant difference between rest and driving conditions after 5 minutes from the start of the driving on the parameters $\alpha$/total and $\beta$/total, and increased level of sympathetic nervous system. But there was no significant difference between different time conditions. The results indicates that physiological changes from simulator sickness can be a bias factor in objective evaluation of human sensibility which also, uses physiological signals. That is, the changes on the parameter $\alpha$/total and $\beta$/total, and on activation level of sympathetic nervous system from simulator sickness can be a bias factor for evaluation of the level of pleasantness and tension. Therefore the effort on improving the analysis by minimizing or eliminating the bias factors should be done for better and accurate sensibility evaluation in simulator environments.

• Journal of information and communication convergence engineering
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• v.11 no.3
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• pp.167-172
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• 2013

Recently, mobile communication systems are suffering from exponentially increasing data traffic. As a promising solution to the increase in data traffic, a coordinated multi-point transmission and reception (CoMP) scheme has been proposed. Although a great deal of research has been done on this new technology, the performance of mobile communication systems with CoMP has not been evaluated properly in a typical indoor environment. To address this, we have developed a system-level simulator and evaluated the performance of mobile communication systems with CoMP. Unlike previous works, we have used an actual antenna pattern in our simulator and link-level results are properly taken into account through link-level abstraction. By using a system-level simulator, we have evaluated the performance of mobile communication systems with CoMP in an indoor environment and found that unlike an outdoor cellular environment, CoMP may not improve the performance of overall mobile communication systems in an indoor environment.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.4
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• pp.476-483
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• 2014

This paper describes the operational analysis results of the bipolar DC distribution system coupled with the distributed generators. The energy management for AC/DC power trade and the operational principle of distributed generators and energy storages were first analyzed by computer simulation with PSCAD/EMTDC software. After then a hardware simulator for the bipolar DC distribution system was built, which is composed of the grid-tied three-level inverter, battery storage, super-capacitor storage, and the voltage balancer. Various experiments with the hardware simulator were carried out to verify the operation of bipolar DC distribution system. The developed simulator has an upper-level controller which operates in connection with the controllers for each distributed generator and the battery energy storage based on CAN communication. The developed hardware simulator are possible to use in designing the bipolar DC distribution system and analyzing its performance experimentally.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.1B
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• pp.71-79
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• 2011

This paper proposes a compiled-code simulator generation system based-on machine description language for efficient design space exploration in designing an embedded system optimized for a specific application. The proposed system generates a compiled-code simulator which maintains the functional accuracy of an event-driven simulator by determining instruction fetch and decoding processes statically. Generated simulator takes instruction-level and cycle-level simulation for estimating performances in embedded core. To show the efficiency of the constructed compiled-code simulator generator, architecture exploration had been performed for the JPEG encoder application. Starting with MIPS R3000 processor for one embedded core, the proposed system can produce the core showing optimized execution time for the application programming. In this process, a huge amount of simulation time has been used. Cycle-level compiled-code simulator has the functional accuracy and shows performance improvement by 21.7% in terms of simulation speed on the average when compared with an event-driven simulator.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.161-164
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• 2000

The architecture of microprocessor for a embedded system should be one that can perform more tasks with fewer instruction codes. The machine codes that high-level language compiler produces are mainly composed of specific ones, and codes that have small size are more frequently used. Extended Instruction Set Architecture (EISC) was proposed for that reason. We have designed pipe-line system for 64 bit EISC microprocessor. function level simulator was made for verification of design and instruction set architecture was also verified by that simulator. The behavioral function of synthesized logic was verified by comparison with the results of cycle-based simulator.

• Proceedings of the KSR Conference
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• 2005.05a
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• pp.175-180
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• 2005

As the high performance computer system increases, improving of reality and usefulness causes the virtual environment of simulator to be used widely as training and assessment tool. Although some domestic companies have developed train driving simulators since about mid of 1990s, accumulation of technology and experience is not yet sufficient compared to foreign makers. This paper describes system composition, training and assessment regimes for high level train driving simulator. When the subsystems are designed, comprehension of train system is emphasized and the functions that simulator should provide are discussed.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.1
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• pp.39-46
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• 2016

According to general architecture of flight simulator made up of several independent rendering display systems, display synchronization problem between them naturally happens. In addition, since the flight simulator is usually implemented in the same networks where network delay is not big concern, it is necessary to consider different factors of existing synchronization technique. Among them, in this paper, we propose a new display synchronization scheme for flight simulator where each system has different rendering capacity. In the proposed scheme, each system is synchronized by considering maximum and minimum frames per second (FPS) while considering level of detail and latency. Also, experimental results are given to demonstrate the suitability of the proposed scheme for display synchronization scheme.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.963-966
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• 2001

The wideband DS-CDMA (W-CDMA) system is one of the candidates for the next generation mobile communication system known as IMT-2000. The important concept of W-CDMA is the introduction of intercell asynchronous operation. In this paper, we design and analyze the system level simulator for the International Mobile Tele communication - 2000 (IMT-2000) 3-rd generation partnership project (3GPP) system. We confirm how the simulator works by BER over different Eb/NO. This study will be expected to use as reference data in the development of asynchronous IMT-2000. In this paper, we analyze a physical layer of W-CDMA system and design a transmitter and receiver by using ADS (Advanced Design System). Also, we simulated a link level performance in Rayleigh fading channel environment. This study will be useful in the analysis and design of W-CDMA system.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.3
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• pp.257-267
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• 2005

The real-time operating system(RTOS) simulator, one of the tools provided by RTOS development environment, allows users to develop and debug application programs even before the target hardware is ready. Thus, most of commercial RTOS development environments provide with RTOS simulator for the purpose. But they are implemented to simulate only functional aspects on a host system, so that it is not possible to estimate execution time of application programs on the target hardware. Since the real-time system has to complete program executions in predetermined time, the RTOS simulator that can estimate the execution time is yeW useful in the development phase. In this study, we develop a machine instruction-level RTOS simulator that is able to estimate execution time of application programs on a target hardware, and prove its functionality and accuracy by using test .programs.