• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(5)
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• pp.171-174
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• 2000

In stead of RF module which has been used conventionally in many remote measurement applications, a new type of remote measurement system based on PCS(Personal communication system) and one chip Microcontroller is proposed in this work. PCS has many advantages with respect to cost reliability, communication quality, and so on. The proposed system consists of three different modules: PCS module, micro-controller module, and sensor module. System configuration as well as illustrative experiments will be described in detail.

• Journal of Microbiology and Biotechnology
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• 제16권8호
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• pp.1229-1235
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• 2006

A lab-on-a-chip (LoC) was designed for simultaneous monitoring of microorganisms, antibiotic residues, somatic cells, and pH in raw milk. The LoC was fabricated from polydimethylsiloxane (PDMS) using microelectromechanical system (MEMS) technology, which consisted of two parts; a protein array and microchannel. The protein array was fabricated by immobilizing five types of antibodies corresponding to two microorganisms, two antibiotic residues, and somatic cells. A sol-gel film was deposited on a glass substrate to immobilize the antibodies. The target analytes in raw milk could be bound with the corresponding antibody by an immunoreaction, and the antigen-antibody complex was detected using fluorescence microscopy. SNARF-dextran was used as a pH indicator, and the SNARF-entrapped hydrogel was attached to the microchannel in the chip. After injecting the milk sample into the channel, the pH was measured by monitoring the change in fluorescence intensity by fluorescence microscopy. The on-chip simultaneous assay of two microorganisms (E. coli O157:H7 and Streptococcus agalactiae), two antibiotic residues (penicillin G and dihydrostreptomycin), and neutrophils was successfully accomplished using the proposed LoC system.

• ETRI Journal
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• 제38권6호
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• pp.1240-1249
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• 2016

With the number of IP cores in a multicore system-on-chip increasing to up to tens or hundreds, the role of on-chip interconnection networks is vital. We propose a networks-on-chip-style bus network as a compromise and redefine the exploration problem to find the best IP tiling patterns and communication path combinations. Before solving the problem, we estimate the time complexity and validate the infeasibility of the solution. To reduce the time complexity, we propose two fast exploration algorithms and develop a program to implement these algorithms. The program is executed for several experiments, and the exploration time is reduced to approximately 1/22 and 7/1,200 at the first and second steps of the exploration process, respectively. However, as a trade-off for the time saving, the time cost (TC) of the searched architecture is increased to up to 4.7% and 11.2%, respectively, at each step compared with that of the architecture obtained through full-case exploration. The reduction ratio can be decreased to 1/4,000 by simultaneously applying both the algorithms even though the resulting TC is increased to up to 13.1% when compared with that obtained through full-case exploration.

• 대한전자공학회논문지SD
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• 제42권2호
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• pp.65-72
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• 2005

공정기술과 EDA 툴의 발전에 따라서 하나의 실리콘 다이(Die)에 많은 IP가 집적되고 멀티프로세서가 포함되는 SoC 구조가 가능해지고 있다 그러나 대부분의 기존 SoC 버스는 공유버스 구조라는 문제점으로 인해 통신의 병목현상이 발생하고 이는 전체 시스템 성능을 저하시키는 요인이 된다. 많은 경우에 멀티프로세서 시스템의 성능은 CPU 자체의 속도보다는 효율적인 통신과 균형있는 연산의 분배가 좌우하게 된다 따라서 충분한 SoC 버스 대역폭(Bandwidth)을 확보하기 위한 하나의 해결책으로 크로스바 라우터(Crossbar Router)를 이용하여 효율적인 온 칩 버스구조인 SoC Network Architecture(SNA)를 제안한다. 제안된 SNA구조는 다중 마스터(multi-master)에 대해 다중 채널(multi-channel)을 제공하여 통신의 병목현상을 크게 줄일 수 있으며 뛰어난 확장성을 지원한다. 제안된 구조에 따라 모델 시스템을 설계하고 시뮬레이션을 진행한 결과 AMBA AHB 버스에 비해 평균 $40\%$ 이상 효율이 증가했다.

• 전자공학회논문지A
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• 제31A권10호
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• pp.161-172
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• 1994

This paper describes the design of a neurochip with on-chip learning capability in hardware with multiple processing elements. A digital architecture is adopted because its flexiblity and accuracy is advantageous for simulating the various application systems. The proposed chip consists of several processing elements to fit the large computation of neural networks, and has on-chip learning capability based on error back-propagation algorithm. It also minimizes the number of blobal control signals for processing elements. The modularity of the system makes it possible to buil various kinds of boards to match the expected range of applications.

• 전기전자학회논문지
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• 제23권4호
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• pp.1203-1207
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• 2019

As the number of IP cores has been increasing in a System-on-Chip (SoC), multiple routers are included in on-chip-networks. Each router has its own arbitration policy and it is difficult to obtain a desired arbitration result by combining multiple routers. Allocating desired bandwidths to the ports across the routers is more difficult. In this paper, a guaranteed bandwidth allocation scheme using an IP-level QoS control is proposed to overcome the limitations of existing local arbitration policies. Each IP can control the priority of a packet depending on the data communication requirement within the allocated bandwidth. The experimental results show that the proposed mechanism guarantees for IPs to utilize the allocated bandwidth in multiple router on-chip-networks. The maximum error rate of bandwidth allocation of the proposed scheme is only 1.9%.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.399-402
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• 2004

This paper presents a system-on-chip prototype implementing a full integration for a portable digital audio system. The chip is composed of a audio processor block to implements audio decoding and voice compression or decompression software, a system control block including 8-bit MCU core and Memory Management Unit (MMU) a low power 16-bit ${\Sigma}{\Delta}$ CODEC, two DC-to-BC converter, and a flash memory controller. In order to support other audio algorithms except Mask ROM type's fixed codes, a novel 16-bit fixed-point DSP core with the program-download architecture is proposed. Funker, an efficient power management technique such as task-based clock management is implemented to reduce power consumption for portable application. The proposed chip has been fabricated with a 4 metal 0.25um CMOS technology and the chip area is about 7.1 mm ${\times}$ 7.1mm with 100mW power dissipation at 2.5V power supply.

• 한국기계가공학회지
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• 제10권3호
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• pp.53-59
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• 2011

In this study, a two-phase closed loop cooling system is desinged and tested for a laptop computer using a FC-72. The cooling system is characterized by a parametric study which determines the effects of existence of a boiling enhancement microstructure, initial system pressure, volume fill ratio of coolant and inclination angle of condenser on the thermal performance of the closed loop. Experimental data show the optium condition when the volume ratio of working fluid is 70%, the pump flowing is 6ml/min, and the inclination angle of condenser is $0^{\circ}$. This research shows the maximum values which can dissipate 33W of chip power with a chip temperature maintained at $95^{\circ}C$.

• 대한전자공학회논문지TE
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• 제37권5호
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• pp.56-61
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• 2000

반도체 공정 기술의 발달은 기하 급수적인 집적도의 증가를 가져오고, 이는 한 칩에 시스템을 모두 집적시키는 시스템 온 칩(SoC : System on Chip) 설계가 가능해지고, 이에 따른 설계 방법의 변화를 요구하고 있다. Soc 설계는 시스템에서 설계 사양(Specification)의 정의가 중요한 요소가 되고 있다. 본 논문에서는 MPEG 오디오 복호기에서 사용되는 IMDCT를 시스템 수준의 실행 가능한 설계 사양(Executable Specification)에 의해 설계하였다.

• 한국멀티미디어학회논문지
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• 제18권2호
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• pp.244-252
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• 2015

This paper describes the design and implementation of a System-on-a-Chip (SoC) for face recognition to use in wearable/mobile products. The design flow starts from the system specification to implementation process on silicon. The entire process is carried out using a FPGA-based prototyping platform environment for design and verification of the target SoC. To ensure that the implemented face recognition SoC satisfies the required performances metrics, time analysis and recognition tests were performed. The motivation behind the work is a single chip implementation of face recognition system for target applications.