• Journal of the Korean Society of Manufacturing Process Engineers
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• v.3 no.2
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• pp.25-31
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• 2004

Machinability in metal cutting processes depends on cutting input conditions such as cutting velocity, feed rate, depth of cut, types of work material and tool shape factors. In this study, to assess chip breaking characteristics of a turning process, an equivalent oblique cutting system to this has been established. And the equivalent effective rake angle was determined using side rake angle, back rake angle and side cutting edge angle of the tool. A non-dimensional parameter, Chip breaking index(CB), was used to assess Chip breaking characteristics of chip in conjunction with the equivalent effective rake angle. In case of positive rake angles of the equivalent effective rake, the back rake angle has little effect on the chip breaking characteristics however, in case of negative ones, the side rake angle has some effect on Chip breaking characteristics.

• The Journal of the Korea Contents Association
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• v.5 no.1
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• pp.229-236
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• 2005

Testing time and power consumption during testing System-On-a-Chip (SOC) are becoming increasingly important as the IP core increases in a SOC. We present a new algorithm to reduce the scan-in power and test data volume using the modified scan latch reordering. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.61-68
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• 2008

This paper introduces an embedded core test wrapper for AMBA based System-on-Chip(SoC) test. The proposed test wrapper is compatible with IEEE 1500 and can be controlled by ARM Test Interface Controller(TIC). We use IEEE 1500 wrapper boundary registers as temporal registers to load test results as well as test patterns and apply a modified scan test procedure. Test time is reduced by simultaneously performing primary input insertion and primary output observation as well as scan-in and scan-out.

• Journal of the Korean Society for Precision Engineering
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• v.12 no.8
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• pp.53-62
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• 1995

In recent years, the rapid development of the machine tool and tough insert has made metal removal rates increase, and automatic system without human supervision requires a higher degree reliability of machining process. Therefore the control of chips is one of the important topics which deserves much attention. The chip classification was made based upon standard deviation of the mean cutting force measured by a tool dynamometer. STS304was chosen as the workpiece which is known as the difficult-to-cut material and mainly saw-toothed chip produced, and the chip type according to the standard deviation of mean cutting force was classified into five categories in this experiment. Long continuous type chip which interrupts the normal cutting process, and damages the operator, tool and workpiece has low standard deviation value, while short broken type chip, which is favourable chip for disposal, has relatively large standard deviation value. In addition, we investigated the possibility that the chip type can be predicted analyzing the relationship between chip type and cutting condition by the trained neural network, and obtained favourable results by which the chip type can be predicted with cutting conditon before cutting process.

• Proceedings of the KIEE Conference
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• 2000.07a
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• pp.215-217
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• 2000

Protective relay play a crucial role in the proper operation of a power system, and the reliable transfer of electrical power. This paper deals with the design and implementation of a digital protective relay on a single chip. Implementation on the FPGA(Field Programmable Gate Array) of the chip of digital protective relay. This protective relaying chip monitors the frequency and the voltage and current of the power system. And report the voltage, the current. the frequency, active power and reactive power.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.2
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• pp.120-126
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• 2009

There are many different types of surface defects on semiconductor Integrated Chips (IC's) caused by various factors during manufacturing process, such as cracks, foreign materials, chip-outs, chips, and voids. These defects must be detected and classified by an inspection system for productivity improvement and effective process control. Among defects, in particular, foreign materials and chips are the most difficult ones to classify accurately. A vision system composed of a carefully designed optical system and a processing algorithm is proposed to detect and classify the defects on QFN(Quad Flat No-leads) packages. The processing algorithm uses features derived from the defect's position and brightness value in the Maximum Likelihood classifier and the optical system is designed to effectively extract the features used in the classifier. In experiments we confirm that this method gives more effective result in classifying foreign materials and chips.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.175-183
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• 2014

In this paper, we present the design and implementation of real-time sound localization based on $0.13{\mu}m$ CMOS process. Time delay of arrival (TDOA) estimation was used to obtain the direction of the sound signal. The sound localization chip consists of four modules: data buffering, short-term energy calculation, cross correlation, and azimuth calculation. Our chip achieved real-time processing speed with full range ($360^{\circ}$) using three microphones. Additionally, we developed a dedicated sound localization circuit (DSLC) system for measuring the accuracy of the sound localization chip. The DSLC system revealed that our chip gave reasonably accurate results in an experiment that was carried out in a noisy and reverberant environment. In addition, the performance of our chip was compared with those of other chip designs.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.3
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• pp.437-443
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• 2007

In this paper, we propose the power-aware test framework for Network-on-Chip, which is based on embedded processor and on-chip network. First, the possibility of using embedded processor and on-chip network isintroduced and evaluated with benchmark system to test the other embeddedcores. And second, a new generation method of test pattern is presented to reduce the power consumption of on-chip network, which is called don't care mapping. The experimental results show that the embedded processor can be executed like the automatic test equipments, and the test time is reduced and the power consumption is reduced up to 8% at the communication components.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.11 no.4
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• pp.147-153
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• 2012

The demands of the large scale machine tools, for instance, such as planomiller, turning machine, boring machine, NC machine, have been gradually increased in recent years. As the performances of machine tools and/or cutting tools are advanced, it is possible to perform high-speed and high-precision cutting works. The effective treatment of wet chip, which is discharged from cutting works, becomes very important problems. Therefore, this study is forced on the design of large scale machine tools using CATIA V5R18 and analysis of cutter, which is considered as essential equipment in large scale machine tools, using MSC.Nastran & MSC.Patran. Especially, the relations between tolerated load of cutter, driving horse power and rpm of driving shaft in chip processing system are investigated through analysis. As the results, the reliability of design could be improved by evaluating simulated numerical values, it showed that tolerated loads of supported part and edged part of cutter are 87,000N and 14,450N, respectively.

• Journal of the Korean Society for Precision Engineering
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• v.23 no.5 s.182
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• pp.155-161
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• 2006

This paper introduces a new type of mechanical tape feeder for chip mounter. The mechanical feeder is composed of a pneumatic linear actuator and a linear feeding module with the application of a cam-slider. As semiconductor chips are getting smaller, PCB assembly makers require the feeder to position the chip with high accuracy. The linear feeding system improves the positioning accuracy of the chip by getting rid of the index error, which brings into existence on the sprocket rotating feeder. It also can make greatly reduce the dumping rate. The dumping error is caused by the impact occurred as the pawl to interrupt ratchet wheel rotation. The paper discusses its mechanism and mechanical performance. The positioning accuracy and the dynamic characteristic were measured for long time operation and analyzed. As a result, the feeder showed very good performance. However, the feeding system was dynamically unstable due to the cover film eliminator that is required to be modified