• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.8
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• pp.91-98
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• 2010

The Korean navy has been using the ICS(Integrated Communication System) to transfer a command, control and information on the naval ship. The major equipment for the ICS has been imported from abroad, so that there were some problems such as lack of logistics support, leaking military secrets. This paper describes considerations for the development and the key technology of the domestic ICS which is developed to solve the problems mentioned above and to integrate various future communication elements on the naval ship.

• Journal of Internet Computing and Services
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• v.21 no.4
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• pp.51-57
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• 2020

Currently, High-efficient video coding (HEVC) has become the most promising video coding technology. However, the implementation of HEVC in video streaming systems is restricted by factors such as cost, design complexity, and compatibility with existing systems. While HEVC is considering deploying to various systems with different reached methods, H264/AVC can be one of the best choices for current video streaming systems. This paper presents an adaptive method for manipulating video streams using video coding on an integrated circuit (IC) designed with a private network processor. The proposed system allows to transfer multimedia data from cameras or other video sources to client. For this work, a series of video or audio packages from the video source are forwarded to the designed IC via HDMI cable, called Tx transmitter. The Tx processes input data into a real-time stream using its own protocol according to the Real-Time Transmission Protocol for both video and audio, then Tx transmits output packages to the video client though internet. The client includes hardware or software video/audio decoders to decode the received packages. Tx uses H264/AVC or HEVC video coding to encode video data, and its audio coding is PCM format. By handling the message exchanges between Tx and the client, the transmitted session can be set up quickly. Output results show that transmission's throughput can be achieved about 50 Mbps with approximately 80 msec latency.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.55 no.1
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• pp.26-30
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• 2006

For the purpose of developing capacitive humidity sensor having interdigital electrodes, interdigital electrode was modeled and simulated to obtain capacitance and sensitivity as a function of geometric parameters like the structural gap and thickness. For the development of ASIC, switched capacitor signal processing circuits for capacitive humidity sensor were designed and simulated by Cadence using $0.25{\mu}m$ CMOS process parameters. The signal processing circuits are composed of amplifier for voltage gain control, and clock generator for sensor driving and switch control. The characteristics of the fabricated sensors are; 1) sensitivity is 9fF/%R.H., 2) temperature coefficient of offset(TCO) is $0.4%R.H./^{\circ}C$, 3) nonlinearity is 1.2%FS, 4) hysteresis is 1.5%FS in humidity range of $3%R.H.{\sim}98%R.H.$. The response time is 50 seconds in adsorption and 70 seconds in desorption. Fabricated process used in this capacitive humidity sensor having interdigital electrode are just as similar as conventional IC process technology. Therefore this can be easily mass produced with low cost, simple circuit and utilized in many applications for both industrial and environmental measurement and control system, such as monitoring system of environment, automobile, displayer, IC process room, and laboratory etc.

• ETRI Journal
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• v.36 no.1
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• pp.31-41
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• 2014

The heterogeneous network (HetNet) has been discussed in detail in the Long-Term Evolution (LTE) and LTE Advanced standards. However, the standardization of High-Speed Packet Access HetNet (HSPA HetNet) launched by 3GPP is pushing at full steam. Interference coordination (IC), which is responsible for dealing with the interference in the system, remains a subject worthy of investigation in regard to HSPA HetNet. In this paper, considering the network framework of HSPA HetNet, we propose a quasi-distributed IC (QDIC) scheme to lower the interference level in the co-channel HSPA HetNet. Our QDIC scheme is constructed as slightly different energy-efficient non-cooperative games in the downlink (DL) and uplink (UL) scenarios, respectively. The existence and uniqueness of the equilibrium for these games are first revealed. Then, we derive the closed-form best responses of these games. A feasible implementation is finally developed to achieve our QDIC scheme in the practical DL and UL. Simulation results show the notable benefits of our scheme, which can indeed control the interference level and enhance the system performance.

• Explosives and Blasting
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• v.22 no.1
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• pp.23-32
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• 2004

터널 발파를 원활히 수행하기 위해서는 암반조건에 적합한 합리적인 설계와 정밀한 천공, 정확한 기폭초시가 기본요소로서 이는 현재 국내 터널 설계.시공 기술 및 기자재의 발달로 만족할 만한 성과를 얻을 수 있다. 특히. 터널발파에서 정확한 기폭초시 부여는 굴진율 및 버럭 파쇄율, 굴착예정선 미려도, 잔여 암반 손상도 등의 시공성에서 뿐만 아니라 소음 및 진동 발생율을 좌우하는 환경적인 측면에서 매우 중요한 요소이다. 기폭요소는 최초 도화선을 활용한 공업뇌관에서 전기뇌관, 비전기식뇌관의 순으로 기폭안전성과 정밀성 면에서 눈부신 성장을 이룩하여 왔으며 특히, 90년대 초에 개발되어 전 세계적으로 최근까지 지속적으로 사용량이 급증하고 있는 전자뇌관은 기폭방식에 일대혁신을 이루었다. 전자기폭 시스템은 기존뇌관의 초시를 결정하는 화약성분의 지연요소 대신에 IC board(전자회로)에 의한 Digital timer로 신호를 발생하여 초시를 결정하는 방식이다. 본 논문에서는 국내 최초로 전자기폭시스템을 활용하여 2003년 9원 23일에서 동년 11월 2일까지 강원도 양구 지역의 $\bigcirc\bigcirc$터널에 전자뇌관을 이용한 시험발파를 실시하였고, 발파에 의한 진동 등을 조사하여 그 효율성을 검토하였다. 이를 위해 전자뇌관의 특성과 장점을 최대한 샅리기 위하여 각공을 발파하는 방식, 즉 1지발에 1공을 발파하는 방식을 채택하고 일반 뇌관과 전자뇌관으로 설계를 하여 각각의 발파효율을 비교하여 보았다. 그 결과 발파진동의 경우 기존뇌관을 이용하여 1공씩을 1지발로 발파를 한 경우에는 18~56%의 진동저감 효과가 있었고. 본선 설계에 의해 진행된 발파에 비하여는 최대 70% 이상의 진동저감 효과가 있는 것으로 나타났다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.5
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• pp.611-618
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• 1993

A common requirement in digital communication systems is the generation of prescribed shape. The purpose of this paper is implement an efficient digital waveform filter by using the look-up table in the RDS(Radio Data System) encoder. And it has been shown that transmitted data can be recovered without an error. In order to implement an efficient waveform filter, the control algorithm is designed. For the purpose of composing an IC, the digital waveform filter is implemented by using the discrete elements. Moreover in this paper it has been proved that the proposed digital waveform filter can be applied to the RDS encoder.

• Journal of IKEEE
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• v.17 no.3
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• pp.254-259
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• 2013

The choice of labeled data in semi-supervised learning algorithm can result in effects on the performance of the resultant classifier. In order to select labeled data required for the training of a semi-supervised learning algorithm, VCNN(Vector Centroid Neural Network) is proposed in this paper. The proposed selection method of label data is evaluated on UCI dataset and caltech dataset. Experiments and results show that the proposed selection method outperforms conventional methods in terms of classification accuracy and minimum error rate.

• The Journal of the Korea Contents Association
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• v.5 no.5
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• pp.17-25
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• 2005

In this paper, we design data transformation interface for the automation of PCB product. The data designed to CAD does not exchange itself for the assembly line, so we construct an automation system which is exchangeable. To do this, we analyze the information of PCB components and construct the Information of IC components as database. We also develope two kinds of algorithm; one is to detect human error and another is to exchange itself for the data which is suitable for PCB assembly line. We design data transformation interface to do addition and revision of the information for PCB assembly line. By automating existing manual processing, we are able to shorten access time and enhance reliability of the data and the efficient assembly line of PCB.

• Proceedings of the KIPE Conference
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• 2003.11a
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• pp.132-136
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• 2003

Generally, PM BLDC drive system is necessary that the three Hall-ICs evenly be distributed around the stator circumference and encoder be installed in case of the 3 phase motor. So, the Hall-ICs are set up in this motor to detect the main flux from the rotor, and the output signal from Hall-ICs is used to drive a power transistor to control the winding current. However, instead of using three Hall-ICs and encoder, we used only two Hall-ICs for the permanent magnet rotor position and for the speed feedback signals, and also for a micro controller of 16-bit type (80C196KC) with the 3 phase PM BLDC whose six stator and two rotor designed. Two Hall-IC Hc and $H_B$ are placed on the endplate at 120 degree intervals, and with these elements, we estimated information of the others phase in sequence through a rotating rotor.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.3
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• pp.144-148
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• 2001

For the purpose of developing capacitive humidity sensor having interdigit electrodes, interdigit electrode was modeled and simulated to obtain capacitance and sensitivity as a function of geometric parameters like the structural gap and thichness. For the development of ASIC, switched capacitor signal conditioning circuits for capacitive humidity sensor were designed and simulated by cadence using 0.25um CMOS process parameters. The signal conditioning circuits are composed of amplifier for voltage gain control, and clock generator for sensor driving and switch control The characteristics of the fabricated sensors are; 1) sensitivity is 9fF/%R.H., 2) temperature coefficient of offset(TCO) is 0.4%R.H./$^{\circ}C$, 3) nonlinearity is 1.2%FS, 4) hysteresis is 1.5%FS in humidity range of 3%R.H. ${\sim}$ 98%R.H.. The response time is 50 seconds in adsorption and 70 seconds in desorption. Fabricated process used in this capacitive humidity sensor having interdigit electrode are just as similar as conventional IC process technology. Therefore this can be easily mass produced with low cost, simple circuit and utilized in many applications for both industrial and environmental measurement and control system, such as monitoring system of environment, automobile, displayer, IC process room, and laboratory etc..