• 전기전자학회논문지
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• 제19권2호
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• pp.176-185
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• 2015

The study aims to a design hybrid frequency synthesizer in spectrum analyzer and to propose new techniques designed for evasion of in-band spurious. The study focuses on calculating the exact location of multiple phase locked loop of hybrid frequency synthesizer and spurious of direct digital synthesizer to evade in-band spurious outside of frequency range that the user wants to see and thereby simulating technique to improve input related spurious of spectrum analyzer for algorithm. The proposed technique is designed to calculate spurious evasion algorithm in central processing system when in-band spurious arises, and to move output frequency of DDS(direct digital synthesizer) into the place where no in-band spurious exists thereby improving performance of frequency synthesizer. The study used simulation and result representation to prove the effectiveness of the proposed technique.

• 한국군사과학기술학회지
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• 제20권5호
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• pp.673-680
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• 2017

In the proposed paper, we designed low noise frequency synthesizer with compact size for Multi-Band. The proposed frequency synthesizer consists of fundamental frequency band(2 GHz) and harmonic frequency band(4 GHz). To improve the phase noise and spurious level of frequency synthesizer, we analyze how the configuration of frequency synthesizer affect the phase noise and design the multi-band's structure. The implemented frequency synthesizer reduce both the phase noise and spurious level. The phase noise is -92.17 dBc/Hz at 1 kHz frequency offset in 2 GHz and -90.50 dBc/Hz at 1 kHz frequency offset in 4 GHz. All spurious signals including fundamental frequency are suppressed at least 20 dBc than the second harmonic frequency.

• 한국위성정보통신학회논문지
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• 제6권1호
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• pp.45-49
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• 2011

본 논문에서 위성통신 단말에 적용할 PLL 주파수 합성기의 잡음 특성을 분석하였고, 주파수 간격(step size)을 작게하면서 저 위상잡음 특성을 갖도록 설계 및 구현하였다. 구현된 주파수 합성기 모듈은 950~1450 MHz 대역에서 -2dBm 이상의 출력을 보였으며, 위상잡음은 10kHz offset에서 -101dBc/Hz로 측정되었다. 주파수 합성기의 위상잡음 특성을 분석한 결과 루프대역 내에서의 위상잡음은 분주기 값을 작게 하기위한 LO의 특성을 따라 감을 알 수 있었다.

• 한국군사과학기술학회지
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• 제17권5호
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• pp.629-636
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• 2014

In the proposed paper, we designed low phase noise frequency synthesizer for Ku-band. The proposed up-mixing frequency synthesizer consists of narrow local oscillation part and variable frequency oscillation part. To improve the phase noise of frequency synthesizer, we analyze how the configuration of frequency synthesizer affect the phase noise. The implemented frequency synthesizer reduce the phase noise. The phase noise is -95.18dBc/Hz at 7kHz frequency offset in 16GHz and -94.27dBc/Hz at 7kHz frequency offset in 16.125GHz.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.978-981
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• 1999

In this paper, an improved integer-N frequency synthesizer that can be synthesized into smaller channel space than input signal frequency is presented. The proposed frequency synthesizer also has an characteristics of fast phase locking time. The frequency synthesizer performed in the manner that it divides various outputs of different phases in VCO by means of dividers that have different control signals respectively and then add the divided signal. In order to confirm the characteristics of proposed frequency synthesizer, behavioral and SPICE simulations are performed using C-language and HSPICE respectively.

• 마이크로전자및패키징학회지
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• 제8권1호
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• pp.19-25
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• 2001

본 연구에서는 디지털 셀룰러용 IF Frequency Synthesizer의 설계, 시뮬레이션 결과 및 측정 결과를 기술하였으며, 공정 및 소자 라이브러리는 AMS사의 0.8 $\mu\textrm{m}$ BiCMOS를 사용하였다. IF Frequency Synthesizer부는 IF 전압제어발진기, 위상검파기, 8분배기, 차지 펌프 및 루프 필터(Loop Filter) 등을 포함하고 있다. 공급전원은 2.7에서 3.6 V이며, IF VCO의 조절전압은 0.5~2.7V이고, 소비전류는 11 mA로 설계결과와 측정결과가 유사한 결과를 보였다.

• ETRI Journal
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• 제29권4호
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• pp.437-444
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• 2007

A CMOS frequency synthesizer block for multi-band orthogonal frequency division multiplexing ultra-wideband systems is proposed. The proposed frequency synthesizer adopts a double-conversion architecture for simplicity and to mitigate spur suppression requirements for out-of-band interferers in 2.4 and 5 GHz bands. Moreover, the frequency synthesizer can consist of the fewest nonlinear components, such as divide-by-Ns and a mixer with the proposed frequency plan, leading to the generation of less spurs. To evaluate the feasibility of the proposed idea, the frequency synthesizer block is implemented in 0.18-${\mu}m$ CMOS technology. The measured sideband suppression ratio is about 32 dBc, and the phase noise is -105 dBc/Hz at an offset of 1 MHz. The fabricated chip consumes 17.6 mA from a 1.8 V supply, and the die-area including pads is $0.9{\times}1.1\;mm^2$.

• 한국군사과학기술학회지
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• 제15권4호
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• pp.450-457
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• 2012

In this paper, we designed low phase noise frequency synthesizer with compact size for High frequency band (Ku-band). The paper addresses merits and demerits of single loop and dual loop frequency synthesizer. The phase noise characteristics of the phase-locked loop frequency synthesizer were predicted based on the analysis for phase noise contribution of noise sources. The proposed model in this paper more accurately predicts the low phase noise frequency synthesizer with compact size for high frequency band.

• International journal of advanced smart convergence
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• 제11권2호
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• pp.53-58
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• 2022

In this paper, w-band frequency synthesizer was developed for frequency-modulated continuous wave (FMCW) radar sensors. To achieve a small size and high performance, We designed and manufactured w-band MMIC chips such as up-converter one-chip, multiplier, DA (Drive Amplifier) MMIC(Monolithic Microwave Integrated Circuit), etc. And interposer technology was applied between the W-band multiplier and the DA MMIC chip. As a result, the measured phase noise was -106.10 dBc@1MHz offset, and the frequency switching time of the frequency synthesizer was less than 0.1 usec. Compared with the w-band frequency synthesizer using purchased chips, the developed frequency synthesizer showed better performance.

• 한국전자파학회논문지
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• 제22권2호
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• pp.258-264
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• 2011

본 논문은 GSM(Global System for Mobile communications)에서 주로 사용되는 Offset-PLL(Phase Locked Loop) 방식을 사용하여 낮은 위상 잡음과 빠른 위상 고정 시간, 우수한 불요파 특성을 갖는 주파수 합성기를 설계 제작하였다. 제안된 주파수 합성기의 구조는 3번의 주파수 하향 변환을 통해 낮은 위상 잡음 갖도록 하였으며, 높은 주파수 해상도를 갖도록 세 개의 offset 주파수중 최종 offset 주파수를 DDS(Direct Digital Synthesizer)를 이용하여 생성하였다. 또한, 빠른 스위칭 속도를 가질 수 있도록 DAC(Digital to Analog Converter)를 사용하였다. DAC 사용에 따른 위상 잡음 열화를 줄이기 위해 DAC 노이즈 제거를 위한 필터를 설계하여 성능을 개선하였다.