• 제목/요약/키워드: Synchronous Error

검색결과 344건 처리시간 0.024초

Dynamic Synchronous Phasor Measurement Algorithm Based on Compressed Sensing

  • Yu, Huanan;Li, Yongxin;Du, Yao
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제14권1호
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    • pp.53-76
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    • 2020
  • The synchronous phasor measurement algorithm is the core content of the phasor measurement unit. This manuscript proposes a dynamic synchronous phasor measurement algorithm based on compressed sensing theory. First, a dynamic signal model based on the Taylor series was established. The dynamic power signal was preprocessed using a least mean square error adaptive filter to eliminate interference from noise and harmonic components. A Chirplet overcomplete dictionary was then designed to realize a sparse representation. A reduction of the signal dimension was next achieved using a Gaussian observation matrix. Finally, the improved orthogonal matching pursuit algorithm was used to realize the sparse decomposition of the signal to be detected, the amplitude and phase of the original power signal were estimated according to the best matching atomic parameters, and the total vector error index was used for an error evaluation. Chroma 61511 was used for the output of various signals, the simulation results of which show that the proposed algorithm cannot only effectively filter out interference signals, it also achieves a better dynamic response performance and stability compared with a traditional DFT algorithm and the improved DFT synchronous phasor measurement algorithm, and the phasor measurement accuracy of the signal is greatly improved. In practical applications, the hardware costs of the system can be further reduced.

4축 전동실린더의 동기제어시스템 설계 (The Synchronous Control System Design for Four Electric Cylinders)

  • 양경욱;변정환
    • 한국전자통신학회논문지
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    • 제11권12호
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    • pp.1209-1218
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    • 2016
  • 4대의 전동실린더를 이용하여 대형 유리판과 같은 부하를 신속하고 안전하게 이송하기 위해서는 동기오차가 허용된 범위 내에서 지속적으로 유지되어야 한다. 본 연구에서는 4대 이상의 전동실린더 간의 동기화에 적용 가능한 동기제어기법이 제안된다. 이 동기제어시스템은 디커플링 구조에 기반을 두고 있으며, 기준모델, 위치제어기 그리고 동기제어기로 구성된다. 기준모델은 각각의 실린더에 대해 상호 분리된 동기오차와 제어입력의 계산이 가능하도록 한다. I-PD형의 위치제어기는 각 실린더가 오버슈트와 입력포화를 일으키지 않고 지령을 추종하도록, 그리고 진상보상기형의 동기제어기는 루프정형을 통해 안정적으로 정밀한 동기가 되도록 설계 된다. 끝으로 토크외란이 인가된 상태에서도 4개의 실린더가 신속하고 안정적으로 동기를 유지하면서 목표지점에 도달됨을 시뮬레이션으로 검증한다.

유도 전동기 센서리스 제어를 위한 동기 각속도 오차 보상기를 갖는 향상된 Programmable LPF 자속 추정기 (Improved Programmable LPF Flux Estimator with Synchronous Angular Speed Error Compensator for Sensorless Control of Induction Motors)

  • 이상수;박병건;김래영;현동석
    • 전력전자학회논문지
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    • 제18권3호
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    • pp.232-239
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    • 2013
  • This paper proposes an improved stator flux estimator through ensuring conventional PLPF to act as a pure integrator for sensorless control of induction motors. Conventional PLPF uses the estimated synchronous speed as a cut-off frequency and has the gain and phase compensators. The gain and phase compensators are determined on the assumption that the estimated synchronous angular speed is coincident with the real speed. Therefore, if the synchronous angular speed is not same as the real speed, the gain and phase compensation will not be appropriate. To overcome the problem of conventional PLPF, this paper analyzes the relationship between the synchronous speed error and the phase lag error of the stator flux. Based on the analysis, this paper proposes the synchronous speed error compensation scheme. To achieve a start-up without speed sensor, the current model is used as the stator flux estimator at the standstill. When the motor starts up, the current model should be switched into the voltage model. So a stable transition between the voltage model and the current model is required. This paper proposes the simple transition method which determines the initial values of the voltage model and the current model at the transition moment. The validity of the proposed schemes is proved through the simulation results and the experimental results.

시각동기를 위한 FPGA 기반의 Inter-Regional Instrument Group-B 디코더 설계 (Design of Inter-Regional Instrument Group-B Decoder Based on FPGA for Time Synchronous)

  • 김용훈;양오
    • 반도체디스플레이기술학회지
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    • 제18권1호
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    • pp.59-64
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    • 2019
  • Recently, time synchronous has become important for satellite launch control facilities, multiple thermal power plants, and power system facilities. Information from time synchronous at each of these industrial sites requires time synchronization to control or monitor the system with correlation. In this paper, IRIG-B codes, which can be used for time synchronous, are used as specifications in IRIG standard 200-16. Signals from IRIG-B120 (Analog), IRIG-B000 (Digital), and one PPS are output from GPS receiver. Using the signal from IRIG-B120 (Analog), it passes through the signal from the analog amplifier and generates one PPS signal using the field-programmable gate array. The FPGA is used cyclone EPM570T100I5N. According to IEEE regulations, the error of one PPS is specified within 1us, but in this paper, the error is within 100ns. The output of the one PPS signal was then compared and tested against the one PPS signal on the GPS receiver to verify accuracy and reliability. In addition, the proposed time synchronous is simple to construct and structure, easy to implement, and provides high time precision compared to typical time synchronous. The output of the one PPS signals and IRIG-B000 signal will be used in many industry sectors.

Compensation of Position Error due to Amplitude Imbalance in Resolver Signals

  • Hwang, Seon-Hwan;Kwon, Young-Hwa;Kim, Jang-Mok;Oh, Jin-Seok
    • Journal of Power Electronics
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    • 제9권5호
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    • pp.748-756
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    • 2009
  • This paper presents a compensation algorithm for position error due to an amplitude imbalance between resolver output signals. Resolvers are typically used to obtain absolute position information for motor drive systems in severe environments. Position error is caused by an amplitude imbalance of the resolver output signals. As a result, the d- and q-axis currents of synchronous reference frame have periodic ripples in the stator fundamental frequency in permanent magnet synchronous motor (PMSM) drive systems. Therefore, this paper proposes a compensation algorithm to reduce the position error generated by the amplitude imbalance. The proposed method does not require any additional hardware, and reduces computation time with a simple integral operation according to rotor position. In addition, the position error can be directly compensated for by the estimated position error. The effectiveness of the proposed compensation algorithm is verified through several simulations and experiments.

영구 자석형 동기모터 속도제어를 위한 비선형 슬라이딩 매니폴드 설계 (Velocity Control of Permanent Magnet Synchronous Motors Using Nonlinear Sliding Manifold)

  • 길정환;신동훈;이영우;정정주
    • 제어로봇시스템학회논문지
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    • 제21권12호
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    • pp.1136-1141
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    • 2015
  • In this paper, we develop a sliding mode controller that uses a nonlinear sliding manifold for the permanent magnet synchronous motor. The proposed controller makes sure that both currents and velocity tracking error converge into equilibria. Nonlinear sliding manifold consists of current dynamics and nonlinear functions which are designed with velocity tracking error and its integrated term. The nonlinear functions are designed to guarantee that velocity tracking error converge into zero. The closed-loop stability is proven by Lyapunov theory. The effectiveness of proposed method is demonstrated by numerical simulation results.

터닝센터에서 메인주축과 서브주축 간의 동기제어를 위한 최적화 연구 (The Optimization of Main and Sub Spindle's Synchronous Control in Turning Center)

  • 김성현;윤강섭;이만형
    • 한국정밀공학회지
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    • 제20권3호
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    • pp.74-81
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    • 2003
  • This paper introduces that the turning center optimizes main and sub spindle's synchronized controller in Open-CNC. In view of optimal design, the mathematical modeling and the frequency domain analysis of spindle's system are simulated. For the minimizing of synchronized error in each spindle's speed, the study of control method and the related control parameter is proposed. By the experiment in prototype machines using the server/client program, the validity of the proposed synchronous error's compensation method is verified.

개방형 CNC에서 주축과 서브 주축 동기를 위한 최적화 연구 (The Optimization of Main and Sub Spindle′s Synchronous In Opening-CNC)

  • 김성현;윤강섭;이만형
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 2002년도 춘계학술대회 논문집
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    • pp.391-394
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    • 2002
  • This paper introduces that the lathe optimize for main and sub spindle's synchronous in Opening-CNC. In view of optimal design, the mathematical modelling and the frequency domain analysis of spindle's system are performed. For the compensation of synchronous error in compounded manufacture process, the optimization method of motor drive's control parameter and the related parameter is proposed. By the experiment in prototype machines using the server/client program, the validity of the proposed method is verified.

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정현파 역기전력 특성을 갖는 브러시리스 동기전동기의 모델링 및 특성해석 (The Modelling and Characteristic Analysis of Brushless Synchronous Motor with Sinusoidal back EMF)

  • 김일남;백수현;김철진;맹인재;윤신용
    • 대한전기학회논문지:전기기기및에너지변환시스템부문B
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    • 제49권6호
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    • pp.380-386
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    • 2000
  • This paper presents the mathematical modelling analysis of Brushless Synchronous Motor(BLSM). The dynamic and the steady state characteristics of BLSM are simulated and analyzed : electromagnetic torque, speed, line voltage, and current. We used mathematical modelling to model of BLSM with sinusoidal back EMF, namely the shaft transformation referencing rotor frame from a, b, c three to produce constant torque like synchronous motor. The experiment result has already similar to compare with simulation result : torque error about 7%, speed error about 5%. The validity of proposed modelling and analysis was confirmed by the experimental result.

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Effects of Array Weight Errors on Parallel Interferene Cancellation Receiver in Uplink Synchronous and Asynchronous DS-CDMA Systems

  • Kim, Yong-Seok;Hwang, Seung-Hoon;Whang, Keum-Chan
    • ETRI Journal
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    • 제26권5호
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    • pp.413-422
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    • 2004
  • This paper investigates the impacts of array weight errors (AWE) in an antenna array (AA) on a parallel interference cancellation (PIC) receiver in uplink synchronous and asynchronous direct sequence code division multiple access (DS-CDMA) systems. The performance degradation due to an AWE, which is approximated by a Gaussian distributed random variable, is estimated as a function of the variance of the AWE. Theoretical analysis, confirmed by simulation, demonstrates the tradeoffs encountered between system parameters such as the number of antennas and the variance of the AWE in terms of the achievable average bit error rate and the user capacity. Numerical results show that the performance of the PIC with the AA in the DS-CDMA uplink is sensitive to the AWE. However, either a larger number of antennas or uplink synchronous transmissions have the potential of reducing the overall sensitivity, and thus improving its performance.

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