• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.8
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• pp.859-866
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• 1988

A high speed frame synchronization system has been realized which generates the frame sync clock from 565Mb/s data stream (the DS-5 digital multiplex hierarchy signal). The design of a frame pattern detector using a parallel detection method brings into low speed operation and resolves the problems due to the high speed operation. The frame synchronization algorithm recommended by CCITT is also realized by designing a sync mode controller. Appropriate design procedures are considered for an efficient hardware design and minimized connection lines. The CAD simulation as well as experiment show that the performance of the newly designed frame synchronization system satisfies the relevant requirements.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.2180-2183
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• 2003

본 논문에서는 광 디스크의 기록 밀도 증가에 따른 신호품질의 열화나 노이즈가 심한 환경에서 DPLL(Digital Phase Locked Loop)의 성능을 개선하기 위한 FD(Frequency Detector)와 PD(Phase Detector) 알고리즘을 제안한다. 제안된 PD 알고리즘은 노이즈에 의해 왜곡되어 RLL 조건을 위배하는 입력신호, 즉 RLL 조건에 의해 결정되는 최소 런 길이보다 주기가 작은 신호에 의해 발생하는 위상오차를 위상오차 보정 시 사용하지 않도록 설계하여 잘못된 정보에 의한 위상오차 보정이 일어나지 않도록 하였다 제안된 FD 알고리즘은 주파수를 추적하기 위해 삽입되는 신호인 Sync 신호의 symmetry 특성을 이용하여 샘플패턴을 검출하도록 하여 기존의 주파수 오차 보정 알고리즘보다 향상된 주파수 추적 성능을 가지도록 하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.10
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• pp.2373-2379
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• 2015

COMS(Communication, Ocean and Meteorological Satellite), the first Korean geostationary meteorological satellite, provides free meteorological information through HRIT/LRIT(High/Low Rate Information Transmission) service. This work presents the development of data receiver circuit that is essential to the implementation of a low-cost meteorological information receiver system. The data receiver circuit processes the data units according to the specification of physical layer and data link layer of HRIT/LRIT service. For this purpose, the circuit consists of a Viterbi decoder, a sync. word detector, a derandomizer, a Reed-Solomon decoder and so on. The circuit also supports PCI express interface to pass the information data on to the host PC. The circuit was implemented on an FPGA(field programmable gate array) and its function was verified through simulations and hardware implementation.

• Journal of Advanced Navigation Technology
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• v.23 no.2
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• pp.97-103
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• 2019

In this paper, we designed and fabricated a receiving modem that can be applied to guided weapons can change real-time targets with little effect of fading. The designed modem consists of synchronous detector, timing error estimator, timing recovery, differential decoder and viterbi decoder, and it's implemented in FPGA so that it can be redesigned and modified according to requirements. The modem board was directly converted from IF frequency to baseband and converted into digital data through ADC. It is confirmed that it is applicable to the guided weapons that changing real-time targets through simulations, measurements and test.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.10C
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• pp.927-932
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• 2006

We Propose a partial response maximum likelihood(PRML) detection method that improves the performance of the high-density optical storage system. It concurrently adjusts the coefficient of equalizer and reference values of branches in Viterbi detector. For the estimation of asymmetric channel characteristics by the tangential tilt, we exploit sync patterns in each data frame. The simulation result shows it improves the Performance up to 4dB at 10-6 BER compared to conventional adaptive PRML.

• Journal of Korean Academy of Oral and Maxillofacial Radiology
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• v.22 no.2
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• pp.273-282
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• 1992

The purpose of this study was to propose the utility which was evaluated the digital image processing and clinical application of the videodensitomery. The experiments were performed with IBM-PC/16bit-AT compatible, video camera(CCdtr55, Sony Co., Japan), an color monitor(MultiSync 3D, NEC, Japan) providing the resolution of 512×480 and 64 levels of gray. Sylvia Image Capture Board for the ADC(analog to digital converter) was used, composed of digitized image from digital signal and the radiographic density was measured by 256 level of gray. The periapical radiograph(Ektaspeed EP-21, Kodak Co., U. S. A) which was radiographed dried human mandible by exposure condition of 70 kVp and 48 impulses, was used for primary X-ray detector. And them evaluated for digitzed image by low and high pass filtering, correlations between aluminum equivalent values and the thickness of aluminum step wedge, aluminum equivalent values of sound enamel, dentin, and alveolar bone, the range of diffuse density for gray level ranging from 0 to 255. The obtained results were as follows: 1. The edge between aluminum steps of digitized image were somewhat blurred by low pass filtering, but edge enhancement could be resulted by high pass filtering. Expecially, edge enhancement between distal root of lower left 2nd molar and alveolar lamina dura was observed. 2. The correlation between aluminum equivalent values and the thickness of aluminum step wedge was intimated, yielding the coefficient of correlation r=0.9997(p<0.00l), the regression line was described by Y=0.9699X+0.456, and coefficient of variation amounting to 1.5%. 3. The aluminum equivalent values of sound enamel, dentin, and alvolar bone were 15.41㎜, 12.48㎜, 10.35㎜, respectively. 4. The range of diffuse density for gray level ranging from 0 to 255 was wider enough than that of photodenstiometer to be within the range of 1-4.9.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.81-88
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• 2004

In this paper, we designed the outer encoder/decoder for the terrestrial DMB that is an advanced digital broadcasting standard, implemented, and verified by using ALTERA FPGA. In the encoder part, it was created the parity bytes (16 bytes) from the input packet (188by1e) of MPEG-2 TS and the encoded data was distributed output by the convolutional interleaver for Preventing burst errors. In the decoder part, It was proposed the algorithm that detects synchronous character suitable to DMB in transmitted data from the encoder. The circuit complexity in RS decoder was reduced by applying a modified Euclid's algorithm. This system has a capability to correct error of the maximum 8 bytes in a packet. After the outer encoder/decoder algorithm was verified by using C language, described in VHDL and implemented in the ALTERA FPGA chips.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.3
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• pp.575-583
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• 2013

In ad hoc networks, a distributed timing synchronization is studied using a firefly-inspired approach. We illuminate the exiting synchronization algorithm based on the theory of pulse-coupled oscillators so that the algorithm can be applied to multi-carrier systems through packet-based communications, where nodes communicate over an orthogonal frequency-division multiple access air interface. As our main result, we introduce a new sync-code detector, which optimally designs both the coupling function and the detection threshold when various network parameters such as the number of nodes in the network and network topology are given a priori. Computer simulations are performed to show the convergence to a synchronized state in realistic network environments.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.45-53
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• 2007

To recover transmitted signal perfectly at DTV receiver, we have to acquire carrier frequency synchronization to compensate pilot signal which located in wrong position and rotated phase. Also, we need a symbol timing synchronization to compensate sampling timing error. Conventionally, to synchronize symbol timing, we use Gardner's scheme which used in multi-level signal. Gardner's scheme is well known for its sampling the timing error signal from every symbol and it makes easy to detect and keep timing sync in multi-path channel. In this paper, to discuss the problem when the received power level is out of range and we cannot get synchronization information. With this problem, we use 2 step procedures. First, we put a received signal power compensation block before Garder's timing error detector. Second, adaptive loop filter to get a fast synchronization information and averaging loop filter's output value to reduce the amount of jitter after synchronization in PLL(Phased Locked Loop) circuit which is used to get a carrier frequency synchronization and symbol timing synchronization. Using the averaging value, we can estimate offset. Based on offset changing ratio, we can adapt adaptive loop filter to carrier frequency and symbol timing synchronization circuit.