• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.93-100
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• 2009

This paper presents a step up four channel DC-DC converter using charge pump voltage doubler structure. Our goal is to design and implement DC-DC converter for capacitive SP4T RF MEMS switch in front end module in wireless transceiver system. Charge pump structure is small and consume low power 3.3V input voltage is boosted by DC-DC Converter to $11.3{\pm}0.1V$, $12.4{\pm}0.1V$, $14.1{\pm}0.2V$ output voltage With 10MHz switching frequency. By using voltage level shifter structure, output of DC-DC converter is selected by 3.3V four channel selection signals and transferred to capacitive MEMS devices. External passive devices are not used for driving DC-DC converter. The total chip area is $2.8{\times}2.1mm^2$ including pads and the power consumption is 7.52mW, 7.82mW, 8.61mW.

• Journal of IKEEE
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• v.11 no.4
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• pp.158-164
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• 2007

In this study, three types of a novel Trench IGBTs(Insulated Gate Bipolar Transistor) are proposed. The first structure has P-collector which is isolated by $SiO_2$ layer to enhance anode-injection-efficiency and enable the device to have a low on-state voltage drop(Von). And the second structure has convex P-base region between both gates. This structure may be effective to distributes electric-field crowded to gate edge. So this structure can have higher breakdown voltage(BV) than conventional trench-type IGBT(TIGBT). The process and device simulation results show improved on-state, breakdown and switching characteristics in each structure. The first one was presented lower on state voltage drop(2.1V) than that of conventional one(2.4V). Also, second structurehas higher breakdown voltage(1220V) and faster turn off time(9ns) than that of conventional structure. Finally, the last one of the proposed structure has combined the two structure (the first one and second one). This structure has superior electric characteristics than conventional structure about forward voltage drop and blocking capability, turnoff characteristics.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.20-27
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• 2010

This paper describes a design of 5-stage pipelined de-blocking filter with power reduction scheme and proposes a efficient memory architecture and filter order for high performance H.264/AVC Decoder. Generally the de-blocking filter removes block boundary artifacts and enhances image quality. Nevertheless filter has a few disadvantage that it requires a number of memory access and iterated operations because of filter operation for 4 time to one edge. So this paper proposes a optimized filter ordering and efficient hardware architecture for the reduction of memory access and total filter cycles. In proposed filter parallel processing is available because of structured 5-stage pipeline consisted of memory read, threshold decider, pre-calculation, filter operation and write back. Also it can reduce power consumption because it uses a clock gating scheme which disable unnecessary clock switching. Besides total number of filtering cycle is decreased by new filter order. The proposed filter is designed with Verilog-HDL and functionally verified with the whole H.264/AVC decoder using the Modelsim 6.2g simulator. Input vectors are QCIF images generated by JM9.4 standard encoder software. As a result of experiment, it shows that the filter can make about 20% total filter cycles reduction and it requires small transposition buffer size.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.65-72
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• 2008

This paper proposes a new dual-loop digital PLL(DPLL) using seamless frequency tracking methods. The dual-loop construction, which is composed of the coarse and fine loop for fast locking time and a switching noise suppression, is used successive approximation register technique and TDC. The proposed DPLL in order to compensate the quality of jitter which follows long-term of input frequency is newly added cord conversion frequency tracking method. Also, this DPLL has VCO circuitry consisting of digitally controlled V-I converter and current-control oscillator (CCO) for robust jitter characteristics and wide lock range. The chip is fabricated with Dongbu HiTek $0.18-{\mu}m$ CMOS technology. Its operation range has the wide operation range of 0.4-2GHz and the area of $0.18mm^2$. It shows the peak-to-peak period jitter of 2 psec under no power noise and the power dissipation of 18mW at 2GHz through HSPICE simulation.

• Journal of the Korean Institute of Intelligent Systems
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• v.3 no.2
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• pp.18-35
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• 1993

The water level control system of the steam generator in a pressurized water reactor and its control problems are analysed. In this work the stable control strategy during the low power operation and transient states is studied. To solve the problem, a fuzzy logic control method is applied as a basic algorithm of the controller. The control algorithm is based on the operator's knowledges and the experiences of manual operation for water level control at the compact nuclear simulator set up in Korea Atomic Energy Research Institute. From a viewpoint of the system realization, the control variables and rules are established considering simpler tuning and the input-output relation. The control strategy includes the dynamic tuning method and employs a substitutional information using the bypass valve opening instead of incorrectly measured signal at the low flow rate as the fuzzy variable of the flow rate during the pressure control mode of the steam generator. It also involves the switching algorithm between the control valves to suppress the perturbation of water level. The simulation results show that both of the fine control action at the small level error and the quick response at the large level error can be obtained and that the performance of the controller is improved.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.4
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• pp.475-483
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• 2012

This paper presents new type of the hybrid supply modulator for the next reconfigurable transmitters. The efficiency of the hybrid supply modulator is one of the most important performance. For enhancement the efficiency, multi-switching structure in the hybrid supply modulator is employed. Additionally, input envelope signal sensing stage is employed for implementation multi-mode operation. To compare the performance of the proposed hybrid supply modulator, the conventional hybrid supply modulator is also designed. The measured efficiency of the proposed hybrid supply modulator is 85 %/84 %/79 % for EDGE/WCDMA/LTE signals which have 384 kHz/3.84 MHz/5 MHz bandwidth, respectively. The efficiency of the proposed hybrid supply modulator is higher than the conventional hybrid supply modulator. Therefore, this structure shows good candidate for the reconfigurable transmitters.

• Journal of the Korean Society of Marine Environment & Safety
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• v.21 no.6
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• pp.759-769
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• 2015

Diode rectifiers are very popular in industry. However, they include large low-order harmonics in the input current and do not satisfy harmonic current content restrictions. To reduce the harmonics to the power system, several methods have been introduced. It is heavy and expensive solution to use passive filters as the solution for high power application. Another solution for the harmonic filter is utilization of active filter, but it is too expensive solution. Diode rectifiers with configurations using switching device have been introduced, but they are very complicated. The combined 12-pulse diode rectifier with the square auxiliary voltage supply has been introduced. It has the advantages that auxiliary circuit is simple and inexpensive compared to other strategies. The advanced auxiliary voltage supply in this thesis is presented as a new solution. When the square auxiliary voltage supply applied, the improvement of THD is 6~60[%] in whole load range. But when the advanced auxiliary voltage supply applied, it shows stable and excellent reduction effect of THD as 57~71[%]. Especially, for the case with 10[%] load factor, reduction effect of THD has little effect as 6[%] in the case of inserting a square auxiliary voltage supply. But when the proposed new solution applied, reduction effect has excellent effect as 71[%]. Theoretical analysis of the combined 12-pulse diode rectifier with the advanced auxiliary voltage supply is presented and control methods of the auxiliary supply is proposed. The reduction in the input current harmonics is verified by simulation using software PSIM.

• Journal of the Korean Society for Railway
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• v.19 no.5
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• pp.617-628
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• 2016

This paper proposes the structure of a smart transformer to improve the performance of the 60Hz main power transformer for rolling stock. The proposed smart transformer is a kind of solid state transformer that consists of semiconductor switching devices and high frequency transformers. This smart transformer would have smaller size than the conventional 60Hz main transformer for rolling stock, making it possible to operate AC electrified track efficiently by power factor control. The proposed structure employs a cascade H-Bridge converter to interface with the high voltage AC single phase grid as the rectifier part. Each H-Bridge converter in the rectifier part is connected by a Dual-Active-Bridge (DAB) converter to generate an isolated low voltage DC output source of the system. Because the AC voltage in the train system is a kind of medium voltage, the number of the modules would be several tens. To control the entire smart transformer, the inner DC voltage of the modules, the AC input current, and the output DC voltage must be controlled instantaneously. In this paper, a control algorithm to operate the proposed structure is suggested and confirmed through computer simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.11
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• pp.83-94
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• 2003

In this paper. a highly linear and low glitch CMOS current mode digital-to-analog converter (DAC) by self calibration bias circuit is proposed. The architecture of the DAC is based on a current steering 6＋4 segmented type and new switching scheme for the current cell matrix, which reduced non-linearity error and graded error. In order to achieve a high performance DAC . novel current cell with a low spurious deglitching circuit and a new inverse thermometer decoder are proposed. The prototype DAC was implemented in a 0.35${\mu}{\textrm}{m}$ n-well CMOS technology. Experimental result show that SFDR is 60 ㏈ when sampling frequency is 32MHz and DAC output frequency is 7.92MHz. The DAC dissipates 46 mW at a 3.3 Volt single power supply and occupies a chip area of 1350${\mu}{\textrm}{m}$ ${\times}$750${\mu}{\textrm}{m}$.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.10
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• pp.319-330
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• 2016

Recently, 3D printing technology has been applied to make a concept model and working mockup of an industrial application. On the other hand, this technology has limited applications in industrial products due to the materials and reliability of the 3D printed product. In this study, the components of a full cord switch module are proposed as a case of a 3D printed component that can be used as a substitute for a short period. These are hub-driven and lever lockup components that have the structural characteristics of breaking down frequently in the emergency operating status. To ensure the structural strength for a substitute period, research of structure optimization was performed because 3D printing technology has a limitation in the materials used. After optimizing the structure variables of the hub-driven component, reasonable results can be drawn in that the safety factors of the left and right switching mode are 1.243 (${\Delta}153.67%$) and 3.156 (${\Delta}404.96%$). The lever lockup component has a structural weak point that can break down easily on the lockup-part because of a cantilever shape and bending moment. The rib structure was applied to decrease the deflection. In addition, optimization of the structural variables was performed, showing a safety factor of 7.52(${\Delta}26%$).