• Journal of Power Electronics
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• v.16 no.3
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• pp.905-914
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• 2016

A high-performance rectifier is introduced in this study. The proposed rectifier combines the conventional pulse width modulation, soft commutation, and instantaneously average line current control techniques to promote circuit performance. The voltage stresses of the main switches in the rectifier are lower than those in conventional rectifier topologies. Moreover, conduction losses of switches in the rectifier are certainly lower than those in conventional rectifier topologies because the power current flow path when the main switches are turned on includes two main power semiconductors and the power current flow path when the main switches are turned off includes one main power semiconductor. The rectifier also adopts a ZCS-PWM auxiliary circuit to derive the ZCS function for power semiconductors. Thus, the problem of switching losses and EMI can be improved. In the control strategy, the controller uses the average current control mode to achieve fixed-frequency current control with stability and low distortion. A prototype has been implemented in the laboratory to verify circuit theory.

• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.189-191
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• 2018

This paper introduces a novel ZVS interleaved totem-pole PFC with the reduced circulating current and the reverse recovery current of the diodes. With the help of a simple auxiliary inductor, both ZVS turn-on of the main switches and soft turn-off of the body diodes can be achieved. In the proposed totem-pole PFC topology since the switching losses and the reverse recovery losses can be significantly reduced, the typical Si MOSFETs can be employed. In addition the circulating current is reduced by adjusting the switching frequency. The proposed PFC topology can be a low cost solution to achieve high efficiency in high power PFC applications. The validity and the feasibility of the proposed topology is verified by the experimental results with a 3.3kW interleaved totem-pole PFC converter.

• Journal of Power Electronics
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• v.16 no.1
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• pp.340-350
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• 2016

A cascaded hybrid multilevel inverter including a reconfiguration technique for low voltage dc distribution applications is proposed in this paper. A PWM generation fault detection and reconfiguration paradigm after an inverter cell fault are developed by using only a single-chip controller. The proposed PWM technique is also modified to reduce switching losses. In addition, the proposed topology can reduce the number of required power switches compared to the conventional cascaded multilevel inverter. The proposed technique is validated by using a 3-kVA prototype. The switching losses of the proposed multilevel inverter are also investigated. The experimental results show that the proposed hybrid inverter can improve system efficiency, reliability and cost effectiveness. The efficiency of proposed system is 97.45% under the tested conditions. The proposed hybrid inverter topology is a promising method for low voltage dc distribution and can be applied for the multiple loads which are required in a data center or telecommunication building.

• Korean Journal of Optics and Photonics
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• v.12 no.2
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• pp.98-102
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• 2001

To analyze the saturating process of $Cr^{4+}:YAG$ crystal and plastic organic dye as the saturable absorber, we have measured the residual optical losses between a free running and a passive Q-switching mode for various optical densities. The undepleted ground state population density and the saturated transmission of the saturable absorber have been evaluated by the additional optical losses with the increased threshold pump energies between two resonators. ill the passive Q-switching mode, the saturable transmission of saturable absorber is less than the maxrnium saturable transmission due to the undepleted ground state population density. nsity.

• Journal of Power Electronics
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• v.18 no.4
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• pp.1255-1267
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• 2018

Parasitic parameters have a larger influence on Silicon Carbide (SiC) devices with an increase of the switching frequency. This limits full utilization of the performance advantages of the low switching losses in high frequency applications. By combining a theoretical analysis with a experimental parametric study, a mathematic model considering the parasitic inductance and parasitic capacitance is developed for the basic switching circuit of a SiC MOSFET. The main factors affecting the switching characteristics are explored. Moreover, a fast-switching double pulse test platform is built to measure the individual influences of each parasitic parameters on the switching characteristics. In addition, guidelines are revealed through experimental results. Due to the limits of the practical layout in the high-speed switching circuits of SiC devices, the matching relations are developed and an optimized layout design method for the parasitic inductance is proposed under a constant length of the switching loop. The design criteria are concluded based on the impact of the parasitic parameters. This provides guidelines for layout design considerations of SiC-based high-speed switching circuits.

• Proceedings of the KIPE Conference
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• 2003.07a
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• pp.227-230
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• 2003

In this paper, a full bridge edge-resonant zero voltage mode based soft-switching PWM DC-DC power converter with a high frequency center tapped transformer link stage is presented from a practical point of view. The power MOSFETS operating as synchronous rectifier devices are implemented in the rectifier center tapped stage to reduce conduction power losses and also to extend the transformer primary side power MOSFETS ZVS commutation area from the rated to zero-load without a requirement of a magnetizing current. The steady-state operation of this phase-shift PWM controlled power converter is described in comparison with a conventional ZVS phase-shift PWM DC-DC converter using the diodes rectifier. Moreover, the experimental results of the switching power losses analysis are evaluated and discussed in this paper. The practical effectiveness of the ZVS phase-shift PWM DC-DC power converter treated here is actually proved by using 2.5kW-32kHz breadboard circuit. An actual efficiency of this converter is estimated in experiment and is achieved as 97$\%$ at maximum.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.4
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• pp.322-329
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• 2012

This paper proposes a non-isolated bidirectional soft-switching converter with high voltage for high step-up/down and high power applications. Compared to the conventional boost converter the proposed converter can achieve approximately doubled voltage gain using the same duty cycle. The voltage ratings of the switch and diode are reduced to half, which result in the use of devices with lower $R_{DS(ON)}$ and on drop leading to reduced conduction losses. Also, voltage ratings of the passive components are reduced, and therefore the total energy volume is reduced to half. Further, the switch is turned on with ZVS in the CCM operation which results in negligible surge caused leading to reduced switching losses. The validity of the proposed converter is proved through a 10kW prototype.

• Journal of Power Electronics
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• v.18 no.4
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• pp.965-974
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• 2018

A new zero-voltage-switching (ZVS) push-pull pulse-width modulation (PWM) converter is proposed in this paper. The wide ZVS condition for all of the switches is obtained by utilizing the energy stored in the output inductor and magnetizing inductance. As a result, the switching losses can be dramatically reduced. A simple auxiliary circuit including two small diodes and one capacitor is added at the secondary side of a high frequency (HF) transformer to reset the primary current during the circulating stage and to clamp the voltage spike across the rectifier diodes, which enables the use of low-voltage and low-cost diodes to reduce the conducting and reverse recovery losses. In addition, there are no active devices or resistors in the auxiliary circuit, which can be realized easily. A detailed steady operation analysis, characteristics, design considerations, experimental results and a loss breakdown are presented for the proposed converter. A 500 W prototype has been constructed to verify the effectiveness of the proposed concept.

• Journal of Power Electronics
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• v.18 no.4
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• pp.1015-1026
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• 2018

A family of dual-DC-input (DI) dual-buck inverters (DBIs) is proposed by employing a DI switching cell as the input of traditional DBIs. Three power ports, i.e. a low voltage DC input port, a high voltage DC input port and an AC output port, are provided by the proposed DI-DBIs. A low voltage DC source, whose voltage is lower than the peak amplitude of the AC side voltage, can be directly connected to the DI-DBI. This supplies power to the AC side in single-stage power conversion. When compared with traditional DBI-based two-stage DC/AC power systems, the conversion stages are reduced, and the power rating and power losses of the front-end Boost converter of the DI-DBI are reduced. In addition, five voltage-levels are generated with the help of the two DC input ports, which is a benefit in terms of reducing the voltage stresses and switching losses of switches. The topology derivation method, operation principles, modulation strategy and characteristics of the proposed inverter are analyzed in-depth. Experimental results are provided to verify the effectiveness and feasibility of the proposed DI-DBIs.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.8
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• pp.1055-1063
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• 2014

Power losses of a 1-stage DC-DC converter and 2-stage DC-DC converter are compared in this paper. A phase-shift full-bridge DC-DC converter is considered as 1-stage topology. This topology has disadvantages in the stress of rectifier diodes because of the resonance between the leakage inductor of the transformer and the junction capacitor of the rectifier diode. 2-stage topology is composed of an LLC resonant full-bridge DC-DC converter and buck converter. The LLC resonant full-bridge DC-DC converter does not need an RC snubber circuit of the rectifier diode. However, there is the drawback that the switching loss of the buck converter is large due to the hard switching operation. To reduce the switching loss of the buck converter, SiC MOSFET is used. This paper analyzes and compares power losses of two topologies considering temperature condition. The validity of the power loss analysis and calculation is verified by a PSIM simulation model.