• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.459-462
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• 2004

In this paper, we present a reducing power consumption of a scheduling for module selection under the time constraint. A a reducing power consumption of a scheduling for module selection under the time constraint execute scheduling and allocation for considering the switching activity. The focus scheduling of this phase adopt Force-Directed Scheduling for low power to existed Force-Directed Scheduling. and it constructs the module selection RT library by in account consideration the mutual correlation of parameters in which the power and the area and delay. when it is, in this paper we formulate the module selection method as a multi-objective optimization and propose a branch and bound approach to explore the large design space of module selection. Therefore, the optimal module selection method proposed to consider power, area, delay parameter at the same time. The comparison experiment analyzed a point of difference between the existed FDS algorithm and a new FDS_RPC algorithm.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.9
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• pp.1240-1248
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• 2013

This paper describes a switching-level operation analysis of BTB(Back-To-Back) converter for HVDC(high voltage DC) application based on MMC(modular multi-level converter). A switching-level operation analysis for BTB converter is very important to understand the converter operation in detail and check the voltage and current transients in each components. However, the development of switching-level simulation model for the actual size BTB Converter is very difficult because the MMC normally has more than 150 sub-modules for each arm. So, a switching level simulation model for the 11-level MMC-based BTB converter was developed with PSCAD/EMTDC software, which has 12 sub-modules for the positive arm and another 12 sub-modules for the negative arm. The DC-voltage balance algorithm, the circulating-current reduction algorithm, the harmonic reduction algorithm, and the redundancy operation algorithm were included in this simulation model. The developed simulation model can be utilized to analyze the MMC-based BTB converter for HVDC application in switching level and to develop the protection scheme for the MMC-based BTB converter for HVDC application.

• Journal of Power Electronics
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• v.19 no.1
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• pp.68-78
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• 2019

The emergence of high voltage conversion applications has resulted in a trend of using semiconductor device series associations. Series associations allow for operation at blocking voltages, which are higher than the nominal voltage for each of the semiconductor devices. The main challenge with these topologies is finding a way to guarantee the voltage balance between devices in both blocking and switching transients. Most of the methods that have been proposed to mitigate static and dynamic voltage unbalances result in increased losses within the device. This paper introduces a new series stack topology, where the voltage unbalances are reduced. This in turn, mitigates the switching losses. The proposed topology consists of a circuit that ensures the soft switching of each device, and one auxiliary circuit that allows for switching energy recovery. The principle for the topology operation is presented and experimental tests are performed for two modules. The topology performs excellently for switching transients on each of the devices. The voltage static unbalances were limited to 10%, while the activation/deactivation delay introduced by the lower module IGBT driver takes place in the dynamic unbalances. Thus, the switching losses are reduced by 40%, when compared to hard switching configurations.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.431-434
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• 2004

The design, simulation, modeling and measurement of a RF switch module for GSM applications were presented in this paper. switch module were simulated by ADS and constructed using a LTCC multi-layer switching circuit and integrated low pass filter, designed to operate in the GSM band. Insertion and return losses at 900 MHz of the low pass filters were designed to lower than 0.3 dB and higher than 12.7 dB respectively. The switch module constructed, contained 10 embedded passives and 3 surface mounted components integrated on $4.6{\times}4.8{\times}1.2$ m volume, 6-layer integrated circuit. The insertion loss of switch module at m MHz were around 11 dB.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.491-492
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• 2008

According to high-speed large scale integration trend of Memory module product, many type of noises, such a reflection, cross-talk simultaneous switching noise, occur on the Package PCB and they make the deterioration of memory module's performance and reliability. As module products have more high efficiency, Hardware of test board and socket has to be considered In test of the high-speed Memory Module. we mainly focused on improvement of Signal integrity Using the High Frequency Test socket that we invented

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.05a
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• pp.686-689
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• 2014

This Paper is about the study that use the IPM(Intelligent Power Module) which is a integrated switching module to drive inverter gates for driving of a multi-pole BLDC(Brushless Direct Current) motors. When designing a inverter using the various manufacturers IPM, it suggests a electronic circuit system to evaluate the electrical and logical characteristics of the IPM with various brands.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.232-235
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• 2001

This paper presents a circuit of the quasi-resonant DC link to achieve soft-switching three phase inverter using intelligent IGBT power module. The soft-switching operation in this circuit is confirmed simulation and experimental results. Its conductive noise is measured for electrical AC motor drive as compared with that of the conventional hard switching inverter.

• The Transactions of the Korea Information Processing Society
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• v.3 no.4
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• pp.947-960
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• 1996

The primary goal for developing high performance ATM switching systems is to minimized the probability of cell loss, cell delay and deterioration of throughput. ATM switching element that is the most suitable for this purpose is the shared buffer memory switch executed by common random access memory and control logic. Since it is difficult to manufacture VLIS(Very Large Scale Integrated circuit) as the number of input ports increased, the used of switching module method the realizes 32$\times$32, 150 Mb/s switch utilizing 8$\times$8, 600Mb/s os 16$\times$16, 150Mb/s unit switch is latest ATM switching technology for small and large scale. In this paper, buffer capacity satisfying total-memory-reduction effect by buffer sharing in a shared buffer memory switch are analytically evalu ated and simulated by computer with cell loss level at traffic conditions, and also features of switching network utilizing the switching module methods in small and large-capacity ATM switching system is analized. Based on this results, the structure in outline of 32$\times$32(4.9Gb/s throughput), 150Mb/s switches under research in many countries is proposed, and eventually, switching-network structure for ATM switching system of small and large and capacity satisfying with above primary goals is suggested.

• Journal of the Korean Data and Information Science Society
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• v.22 no.4
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• pp.735-740
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• 2011

In recent, electronic devices were able to develop and focus for ultra-compact size, intelligence, multifunction and broadband. Their SMPS is realized to ultra-compact size, light weight, high efficiency, high reliability, low noises. The power module which can be used to supply DC output from a commercial power supply (85 to 265 VAC). A switching power supply can be made easily by adding simply external circuit, such as microcontroller, a relay, etc. It would be apply to mostly electronic devices, and fit the global project "Saving energy". But we need to statistical analysis for a quality and performance about a load and an output voltage in product.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.793-794
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• 2011

This paper presents a method of the circuit design of the multiple-valued digital logic switching functions based on the modular techniques. Fisr of all, we introduce the necessity, background and concepts of the modular design techniques for the digital logic systems. Next, we discuss the definitions that are used in this paper. For the purpose of the circuit design for the multiple-valued digital logic switching functions, we discuss the extraction of the partition functions. Also we describe the construction method of the building block, that is called the modules, based on each partition functions. And we apply the proposed method to the example, we compare the results with the results of the earlier methods. In result, we decrease the control functions, it means that we obtain the effective cost in the digital logic design for any other earlier methods. In the future research, we require the universal module that traet more partition functions and more compact module.