• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.45-52
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• 2005

A systolic array formed by interconnecting a set of identical data-processing cells in a uniform manner is a combination of an algorithm and a circuit that implements it, and is closely related conceptually to arithmetic pipeline. High-performance computation on a large array of cells has been an important feature of systolic array. To achieve even higher degree of concurrency, it is desirable to make cells of systolic array themselves systolic array as well. The structure of systolic array with its cells consisting of another systolic array is to be called super-systolic array. This paper proposes a scalable bit-level super-systolic amy which can be adopted in the VLSI design including regular interconnection and functional primitives that are typical for a systolic architecture. This architecture is focused on highly regular computational structures that avoids the need for a large number of global interconnection required in general VLSI implementation. A bit-level super-systolic FIR filter is selected as an example of bit-level super-systolic array. The derived bit-level super-systolic FIR filter has been modeled and simulated in RT level using VHDL, then synthesized using Synopsys Design Compiler based on Hynix $0.35{\mu}m$ cell library. Compared conventional word-level systolic array, the newly proposed bit-level super-systolic arrays are efficient when it comes to area and throughput.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.4
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• pp.285-292
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• 2007

SoC which deploys software modules as well as hardware IPs on a single chip is a major revolution taking place in the implementation of a system design, and high-level synthesis is an important process of SoC design methodology. Recently, SPARK parallelizing high-level synthesis software tool has been developed. It takes a behavioral ANSI-C code as an input, schedules it using code motion and various code transformations, and then finally generates synthesizable RTL VHDL code. Although SPARK employs various loop transformation algorithms, the synthesis results generated by SPARK are not acceptable for basic signal and image processing algorithms with nested loop. In this paper we propose a SoC platform with an application-specific PLD targeting local operations which are feature of many loop algorithms used in signal and image processing, and demonstrate design process which maps behavioral specification with nested loops written in a high-level language (ANSI-C) onto 2D systolic array. Finally the derived systolic array is implemented on the proposed application-specific PLD of SoC platform.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2003.06a
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• pp.280-283
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• 2003

어레이 셀 내의 연산에 대한 고성능 처리는 시스톨릭 어레이의 중요한 특징이다. 본 논문에서는 시스톨릭 어레이 구조 내 셀이 또 다른 시스톨릭 어레이 구조를 가지는 슈퍼 시스톨릭 어레이 구조를 제안하고, 그 예로 비트 레블 슈퍼 시스톨릭 정렬기의 설계 및 구현에 대하여 기술한다. 먼저 정규순환방정식으로 표현된 정렬 알고리즘으로부터 워드 레블 1차원 평면 시스톨릭 어레이를 유도한 후 유도된 워드 레블 시스톨릭 어레이를 슈퍼 시스톨릭 어레이로 변환한다. 위의 과정으로 유도된 비트 레블 슈퍼 시스톨릭 정렬기를 RT수준에서 VHDL로 모델링 하여 동작을 검증하였으며, 검증된 비트 레블 슈퍼 시스톨릭 정렬기는 Hynix에서 제공되는 0.35$\mu\textrm{m}$ 셀 라이브러리와 FPGA V200E칩을 사용하여 합성 및 구현되었다.