• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.1
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• pp.139-146
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• 2003

In this paper we demonstrate a cryptanalysis of the stream cipher LILI-128. Our approach to analysis on LILI-128 is to solve an overdefined system of multivariate equations. The LILI-128 keystream generato $r^{[8]}$ is a LFSR-based synchronous stream cipher with 128 bit key. This cipher consists of two parts, “CLOCK CONTROL”, pan and “DATA GENERATION”, part. We focus on the “DATA GENERATION”part. This part uses the function $f_d$. that satisfies the third order of correlation immunity, high nonlinearity and balancedness. But, this function does not have highly nonlinear order(i.e. high degree in its algebraic normal form). We use this property of the function $f_d$. We reduced the problem of recovering the secret key of LILI-128 to the problem of solving a largely overdefined system of multivariate equations of degree K=6. In our best version of the XL-based cryptanalysis we have the parameter D=7. Our fastest cryptanalysis of LILI-128 requires $2^{110.7}$ CPU clocks. This complexity can be achieved using only $2^{26.3}$ keystream bits.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1210-1217
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• 2004

LILI-II stream cipher is an upgraded version of the LILI-128, one of candidates in NESSIE. Since the algorithm is a clock-controlled, the speed of the keystream data is degraded structurally in a clock-synchronized hardware logic design. Accordingly, this paper proposes a 4-bit parallel LFSR, where each register bit includes four variable data routines for feedback or shifting within the LFSR. furthermore, the timing of the proposed design is simulated using a Max+plus II from the ALTERA Co., the logic circuit is implemented for an FPGA device (EPF10K20RC240-3), and apply to the Lucent ASIC device (LV160C, 0.13${\mu}{\textrm}{m}$ CMOS ＆ 1.5v technology), and it could achieve a throughput of about 500 Mbps with a 0.13${\mu}{\textrm}{m}$ semiconductor for the maximum path delay below 1.8㎱. Finally, we propose the m-parallel implementation of LILI-II, throughput with 4, 8 or 16 Gbps (m=8, 16 or 32).

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2001.05a
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• pp.77-83
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• 2001

In recent years, the AES in North America and the NESSIE project in Europe have been in progress. Six proposals have been submitted to the NESSIE project including the LILI-128 by Simpson in Australia in the synchronous stream cipher category. These proposals tend towards a design with parallelism of the algorithms in order to facilitate speed-up. In this paper, we consider the PS-LFSR and propose the effective implementation of various nonlinear combiners: memoryless-nonlinear combiner, memory-nonlinear combiner, nonlinear filter function, and clock-controlled function. Finally, we propose m-parallel SUM-BSG and LILI-l28's parallel implementation as examples, and we determine their securities and performances.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4A
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• pp.301-309
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• 2002

In this paper, we propose the effective implementation of various nonlinear combiners using by PS-LFSR: m-parallel memoryless-nonlinear combiner, m-parallel memory-nonlinear combiner, m-parallel nonlinear filter function, and m-parallel clock-controlled function. Finally, we propose m-parallel LILI-128 stream cipher as an example of the parallel implementation, and we determine its cryptographic security and performance.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.3
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• pp.23-32
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• 2001

Since the LILI-128 cipher is a clock-controlled keystream generator, the speed of the keystream data is degraded in a clock-synchronized hardware logic design. Basically, the clock-controlled $LFSR_d$ in the LILI-128 cipher requires a system clock that is 1 ~4 times higher. Therefore, if the same clock is selected, the system throughput of the data rate will be lowered. Accordingly, this paper proposes a 4-bit parallel $LFSR_d$, where each register bit includes four variable data routines for feed feedback of shifting within the $LFSR_d$ . Furthermore, the timing of the propose design is simulated using a $Max^+$plus II from the ALTERA Co., the logic circuit is implemented for an FPGA device (EPF10K20RC240-3), and the throughput stability is analyzed up to a late of 50 Mbps with a 50MHz system clock. (That is higher than the 73 late at 45 Mbps, plus the maximum delay routine in the proposed design was below 20ns.) Finally, we translate/simulate our FPGA/VHDL design to the Lucent ASIC device( LV160C, 0.13 $\mu\textrm{m}$ CMOS & 1.5v technology), and it could achieve a throughput of about 500 Mbps with a 0.13$\mu\textrm{m}$ semiconductor for the maximum path delay below 1.8ns.