• Electronics and Telecommunications Trends
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• v.19 no.2 s.86
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• pp.138-146
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• 2004

시스템 연결에 사용되는 프로토콜이 고속, 직렬화 됨에 따라 CDR이 내장된 SERDES 칩의 사용이 늘어나고 있다. 이에 Xilinx 나 Altera 사 등 FPGA 업체들이 SERDES를 FPGA 내장시킨 제품을 출시하기 시작하였다. 이러한 SERDES 임베디드 FPGA는 PCB 설계의 단순화와 신호무결성의 큰 이점이 있다. 본 고에서는 Altera 사의 SERDES 임베디드 FPGA, Stratix-GX 디바이스의 기가비트 트랜시버 ALTGXB 블록의 테스트에 관해 살펴본다.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.4
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• pp.41-49
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• 2004

In this paper, a design and measurement method for FPGA embedded gigabit-transceiver is presented. Altera's Stratix GX device which is general purpose transceiver called GXB was used for implementing PCI Express transceiver. PCI Express is the generation high performance serial I/O bus used to interconnect peripheral devices. After GXB was set follow by PCI Express specifications, the design has been verified by timing simulation and implemented as hardware. We tested it as follow. First GXB internal digital and analog block test second GXB transmitter signal integrity test called Eye mask test, third GXB high-speed serial I/O buffer and on-chip termination test and the last GXB protocol test. This paper shows all the design and measurement procedure about FPGA embedded gigabit-transceiver.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.27-33
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• 2011

Recently many display devices support the digital display interface as display market growth. DisplayPort is a next generation display interface at the PC, projector and high definition content applications in more widely used connection solution development. This paper implements multiple streams based on the behavior of the main link that is suitable for the display port v1.1a standard. The limit point of Displayport, interface between the Sink Device and Sink Device is also implemented. And two or more differential image data are enable to output the result through four Lanes stated in display port v1.1a, of two or more display devices without the addition of a separate Lane. The Multiple Video Streaming Controller is implemented with 6,222 ALUTs and 6,686 register, 999,424 of block memory bits synthesized using Quartus II at Altera Audio/Video Development board (Stratix II GX FPGA Chip).