• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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• pp.155.2-155.2
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• 2013

Strain-relaxed SiGe layer on Si substrate has numerous potential applications for electronic and opto- electronic devices. SiGe layer must have a high degree of strain relaxation and a low dislocation density. Conventionally, strain-relaxed SiGe on Si has been manufactured using compositionally graded buffers, in which very thick SiGe buffers of several micrometers are grown on a Si substrate with Ge composition increasing from the Si substrate to the surface. In this study, a new plasma process, i.e., the combination of PIII&D and HiPIMS, was adopted to implant Ge ions into Si wafer for direct formation of SiGe layer on Si substrate. Due to the high peak power density applied the Ge sputtering target during HiPIMS operation, a large fraction of sputtered Ge atoms is ionized. If the negative high voltage pulse applied to the sample stage in PIII&D system is synchronized with the pulsed Ge plasma, the ion implantation of Ge ions can be successfully accomplished. The PIII&D system for Ge ion implantation on Si (100) substrate was equipped with 3'-magnetron sputtering guns with Ge and Si target, which were operated with a HiPIMS pulsed-DC power supply. The sample stage with Si substrate was pulse-biased using a separate hard-tube pulser. During the implantation operation, HiPIMS pulse and substrate's negative bias pulse were synchronized at the same frequency of 50 Hz. The pulse voltage applied to the Ge sputtering target was -1200 V and the pulse width was 80 usec. While operating the Ge sputtering gun in HiPIMS mode, a pulse bias of -50 kV was applied to the Si substrate. The pulse width was 50 usec with a 30 usec delay time with respect to the HiPIMS pulse. Ge ion implantation process was performed for 30 min. to achieve approximately 20 % of Ge concentration in Si substrate. Right after Ge ion implantation, ~50 nm thick Si capping layer was deposited to prevent oxidation during subsequent RTA process at $1000^{\circ}C$ in N2 environment. The Ge-implanted Si samples were analyzed using Auger electron spectroscopy, High-resolution X-ray diffractometer, Raman spectroscopy, and Transmission electron microscopy to investigate the depth distribution, the degree of strain relaxation, and the crystalline structure, respectively. The analysis results showed that a strain-relaxed SiGe layer of ~100 nm thickness could be effectively formed on Si substrate by direct Ge ion implantation using the newly-developed PIII&D process for non-gaseous elements.

• 한국진공학회지
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• 제6권S1호
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• pp.47-52
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• 1997

Metastable pseudomorphic GeSi layers grown by vapor phase epitaxy on Si(100) substrates were implanted at room temperature. The implantations were performed with 90 KeV As ions to a dose of $1\times 10^{13}\;\textrm{cm}^2$ for $Ge_{0.08}Si_{0.92}$ layers and 709 keV $BF_2^+$ ions to a dose of $3\times 10^{13}\;\textrm{cm}^2$ for $Ge_{0.06}Si_{0.94}$layers. The samples were subsequently annealed for short 10-40 s durations in a lamp furnace with a nitrogen ambient or for a long 30 min period in a vacuum tube furnace. For $Ge_{0.08}Si_{0.92}$samples annealed for a 30 min-longt duration at $700^{\circ}C$ the dopant activation can only reach 50% without introducing significant strain relaxaion whereas samples annealed for short 40s periods (at $850^{\circ}C$) can achieve more than 90% activation without a loss of strain, For $Ge_{0.06}Si_{0.94}$samples annealed for either 40s or 30min at $800^{\circ}C$ full electrical activation of the boron is exhibited in the GeSi epilayer without losing their strain. However when annealed at $900^{\circ}C$ the strain in both implanted and unimplanted layers is partly relaxed after 30min whereas it is not visibly relaxed after 40s.

• 한국전기전자재료학회논문지
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• 제21권1호
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• pp.44-48
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• 2008

Hole mobility characteristics of two representative biaxially strained SiGe/Si structures with high Ge contents are studied, They are single channel ($Si/Si_{1-x}Ge_x/Si$ substrate) and dual channel ($Si/Si_{1-y}Ge_y/Si_{1-x}Ge_x/Si$ substrate), where the former consists of a relaxed SiGe buffer layer with 60 % Ge content and a tensile-strained Si layer on top, and for the latter, a compressively strained SiGe layer is inserted between two layers, Owing to the hole mobility performance between a relaxed SiGe film and a compressive-strained SiGe film in the single channel and the dual channel, the hole mobility behaviors of two structures with respect to the Si cap layer thickness shows the opposite trend, Hole mobility increases with thicker Si cap layer for single channel structure, whereas it decreases with thicker Si cap layer for dual channel. This hole mobility characteristics could be easily explained by a simple capacitance model.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권4호
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• pp.367-380
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• 2013

In this paper, an analytical threshold voltage model is developed for a short-channel double-material-gate (DMG) strained-silicon (s-Si) on silicon-germanium ($Si_{1-X}Ge_X$) MOSFET structure. The proposed threshold voltage model is based on the so called virtual-cathode potential formulation. The virtual-cathode potential is taken as minimum channel potential along the transverse direction of the channel and is derived from two-dimensional (2D) potential distribution of channel region. The 2D channel potential is formulated by solving the 2D Poisson's equation with suitable boundary conditions in both the strained-Si layer and relaxed $Si_{1-X}Ge_X$ layer. The effects of a number of device parameters like the Ge mole fraction, Si film thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been analyzed for gate-length ratio and amount of strain variations. The validity of the present 2D analytical model is verified with ATLAS$^{TM}$, a 2D device simulator from Silvaco Inc.

• 한국진공학회:학술대회논문집
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• 한국진공학회 1998년도 제14회 학술발표회 논문개요집
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• pp.156-157
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• 1998

It is a diffcult and challenging pproblem to control the growth of eppitaxial films. Heteroeppitaxy is esppecially idfficult because of the lattice mismatch between sub-strate and depposited layers. This mismatch leads usually to a three dimensional(3D) island growth. But the use of surfactants such as As, Sb, and Bi can be beneficial in obtaining high quality heteroeppitaxial films. In this study medium energy ion scattering sppectroscoppy(MEIS) was used in order to reveal the growth mode of Ge on Si(001) and the strain of depposited film without and with dynamically supplied atomic hydrogen at the growth thempperature of 35$0^{\circ}C$. It was ppossible to control the growth mode from layer-by-layer followed by 3D island to layer-by-layer by controlling the hydrogen flux. In the absent of hydro-gen the film grows in the layer-by-layer mode within the critical thickness(about 3ML) and the 3D island formation is followed(Fig1). The 3D island formation is suppressed by introducing hydrogen resulting in layer-by-layer growth beyond the critical thickness(Fig2) We measured angular shift of blocking dipp in order to obtain the structural information on the thin films. In the ppressence of atomic hydrogen the blocking 야 is shifted toward higher scattering angle about 1。. That means the film is distorted tetragonally and strained therefore(Fig4) In other case the shift of blocking dipp at 3ML is almost same as pprevious case. But above the critical thickness the pposition of blocking dipp is similar to that of Si bulk(Fig3). It means the films is relaxed from the first layer. There is 4.2% lattice mismatch between Ge and Si. That mismatch results in about 2。 shift of blocking dipp. We measured about 1。 shift. This fact could be due to the intermixing of Ge and Si. This expperimental results are consistent with Vegard's law which says that the lattice constant of alloys is linear combination of the lattic constants of the ppure materials.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.130-130
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• 2011

최근 반도체 메모리 산업의 발전과 동시에 발생되는 문제들을 극복하기 위한 새로운 기술들이 요구되고 있다. DRAM (dynamic random access memory) 의 경우, 소자의 크기가 수십 나노미터 영역으로 줄어들면서, 단채널 효과에 의한 누설전류와 소비전력의 증가 등이 문제가 되고 있다. 하나의 캐패시터와 하나의 트랜지스터로 구성된 기존의 DRAM은, 소자의 집적화가 진행 되어 가면서 정보저장 능력이 감소하는 것을 개선하기 위해, 복잡한 구조의 캐패시터 영역을 요구한다. 이에 반해 하나의 트랜지스터로 구성되어 있는 1T-DRAM의 경우, 캐패시터 영역이 없는 구조적인 이점과, SOI (silicon-on-insulator) 구조의 기판을 사용함으로써 뛰어난 전기적 절연 특성과 기생 정전용량의 감소, 그리고 기존 CMOS (complementary metal oxide semiconductor) 공정과의 호환성이 장점이다. 또한 새로운 물질 혹은 구조를 적용하여, 개선된 전기적 특성을 통해 1T-DRAM의 메모리 특성을 향상 시킬 수 있다. 본 연구에서는, SOI와 SGOI (silicon-germanium-on-insulator) 및 sSOI (strained-si-on-insulator) 기판을 사용한 MOSFET을 통해, strain 효과에 의한 전기적 특성 및 메모리 특성을 평가 하였다. 그 결과 strained-Si층과 relaxed-SiGe층간의 tensile strain에 의한 캐리어 이동도의 증가를 통해, 개선된 전기적 특성 및 메모리 특성을 확인하였다. 또한 채널층의 결함이 적은 sSOI 기판을 사용한 1T-DRAM에서 가장 뛰어난 특성을 보였다.

• 한국자기학회지
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• 제12권5호
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• pp.184-188
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• 2002

수직자기이방성을 가지는 Cu/Ni/Cu(002)/Si(100) 자성박막을 전자빔 증발법을 이용하여 초고진공에서 증착 하였다. 증착 시 RHEED로 측정 한 결과 실리콘 기판 위에 자성박막이 적층성장되었음을 확인하였다. 이러한 Cu/Ni/Cu(001)/Si(100) 자성박막에 1 MeV C 이온을 이온선량 2$\times$$10^{16}$ ions/$\textrm{cm}^2$로 조사한 후 MOKE로 자기이력곡선을 측정한 결과 이온 조사에 의해 자화용이축이 수직에서 수평방향으로 변화되었음을 확인하였다 포항 방사광가속기를 이용하여 X-선 반사도와 Grazing Incident X-ray diffraction(GE) 분석을 수행한 결과 첫 번째 Cu층과 Ni층 사이의 계면은 이온 조사 후 거칠기는 증가하였으나, Cu와 Ni의 전자밀도의 대비는 더욱 명확해졌다. 그리고, 증착 후 Cu와 Ni원자의 격자 상수 차이에 의해 Ni층이 가지고 있었던 strain은 이온 조사 후 완화되었음을 알 수 있었다. 끝으로, 이온조사 시 자성특성 변화와 직접적인 관계가 있는 strain 완화, 계면 혼합층(혹은 새로운 상)등이 생성되는 기구를 탄성충돌 및 비탄성충돌에 의한 열화학적 구동력으로 규명하였다.