• Journal of Institute of Control, Robotics and Systems
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• v.15 no.5
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• pp.488-495
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• 2009

This paper presents a fast feature extraction method for autonomous mobile robots utilizing parallel processing and based on OpenMP, SSE (Streaming SIMD Extension) and CUDA programming. In the first step on CPU version, the algorithms and codes are optimized and then implemented by parallel processing. The parallel algorithms are debugged to maintain the same level of performance and the process for extracting key points and obtaining dominant orientation with respect to key points is parallelized. After extraction, a parallel descriptor via SSE instructions is constructed. And the GPU version also implemented by parallel processing using CUDA based on the SIFT. The GPU-Parallel descriptor achieves an acceleration up to five times compared with the CPU-Parallel descriptor, but it shows the lower performance than CPU version. CPU version also speed-up the four and half times compared with the original SIFT while maintaining robust performance.

• Korean Journal of Applied Biomechanics
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• v.29 no.2
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• pp.71-77
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• 2019

Objective: The aim of this study was to investigate postural control strategies on smart phone use during gait in over 50-year-old adults. Method: 8 elderly subjects (age: $55.5{\pm}3.29yrs$, height: $159.75{\pm}4.20cm$, weight: $62.87{\pm}8.44kg$) and 10 young subjects (age: $23.8{\pm}3.19yrs$, height: $158.8{\pm}5.97cm$, weight: $53.6{\pm}5.6kg$) participated in the study. They walked at a comfortable pace in a gaitway of ~8 m while: 1) reading text on a smart phone, 2) typing text on a smart phone, or 3) walking without the use of a phone. Gait parameters and kinematic data were evaluated using a three-dimensional movement analysis system. Results: The participants read or wrote text messages they walked with: slower speed; lesser stride length and step width; greater flexion range of motion of the head; more flexion of the thorax in comparison with normal walking. Conclusion: Texting or reading message on a smart phone while walking may pose an additional risk to pedestrians' safety.

• The Journal of Korean Physical Therapy
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• v.36 no.1
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• pp.27-32
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• 2024

Purpose: This study was conducted to verify the effect of applying a pressure biofeedback unit on walking ability and knee joint function while performing knee joint extensor strengthening exercises using resistance exercise equipment in total knee replacement (TKR) patients. Methods: This study was conducted on twelve patients receiving rehabilitation treatment after being admitted to a rehabilitation hospital post-TKR. Of these, six were allocated to a feedback group with a pressure biofeedback unit, and the other 6 were allocated to a control group without a pressure biofeedback unit. The subjects performed an exercise program for 45 minutes per session, five times a week, for two weeks. Walking ability and knee joint function were evaluated and analyzed before and after exercise. Results: The feedback group showed significantly better improvements in walking speed, gait cycle, step length on the non-operation side, time on the foot on the operation side, K-WOMAC stiffness, and K-WOMAC function than the control group (p<0.05). Conclusion: When strengthening the knee joint extensor muscles using resistance exercise equipment in TKR patients, the provision of a pressure biofeedback unit was found to improve walking ability and knee joint function by inducing concentric-eccentric contraction of the knee joint extensor muscles. Therefore, the study shows that exercise based on the provision of a pressure biofeedback unit should be considered when strengthening knee joint extensor muscles to improve the walking ability and knee joint function of TKR patients in clinical practice.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.431-441
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• 2003

This paper presents the design of 32 bit microprocessor for a sequence control using a field programmable gate array(FPGA). The microprocessor was designed by a VHDL with top down method, the program memory was separated from the data memory for high speed execution of sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32 bits. And the real time debug operation was implemented for easeful debugging the designed processor with a single step run, PC break point run, data memory break point run. Also in this designed microprocessor, pulse instructions, step controllers, master controllers, BM and BCD type arithmetic instructions, barrel shift instructions were implemented for sequence logic control. The FPGA was synthesized under a Xilinx's Foundation 4.2i Project Manager using a V600EHQ240 which contains 600,000 gates. Finally simulation and experiment were successfully performed respectively. For showing good performance, the designed microprocessor for the sequence logic control was compared with the H8S/2148 microprocessor which contained many bit instructions for sequence logic control. The designed processor for the sequence logic showed good performance.

• Journal of Advanced Marine Engineering and Technology
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• v.33 no.8
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• pp.1129-1136
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• 2009

The paper presents the performance characteristics for a cooling system using EEV. The water cooler was used to reduce thermal deformation and contraction due to high speed of machine tools and the EEV was used for capacity control for water cooler. The apparatus was designed for hot-gas bypass system which a hot-gas can flows from outlet of compressor to the inlet of evaporator. This experiment is the intermediary study for precise temperature control through PID control. The results show that the evaporator pressure increased and refrigeration capacity decreased as the EEV opening step of hot-gas bypass increased. These results can be used as basic data for the design of effective water cooler.

• The Transactions of the Korea Information Processing Society
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• v.5 no.5
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• pp.1345-1356
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• 1998

Prolog tailoring technique, an optimization method to improve the execution speed of a procedure, is proposed in this paper. When a procedure is frequently and repeatedly called and the machine has a lot of callee-saved registers, optimizing prolog and epilog can become an important step of optimization. Epilg tailoring supported by IBM XL C Compiler has been known to improve procedure's execution speed by reducing register restore instructions on execution paths, but no algorithms for prolog tailoring has been proposed yet. The prolog generated by the prolog tailoring algorithm proposed in this paper executes considerably smaller number of register save instructions at run-time. This means the total number of instructions to be executed is decreased resulting in an improvement on the procedure's execution speed. To maintain the correctness of code, prolog code should not be inserted inside diamond structures of loop structures. This paper proposes a prolog tailoring technique which generates register save instructions at the best position in a control flow graph while not allowing the insertion of any prolog code inside diamond structures of loop structures.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2013.06a
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• pp.299-300
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• 2013

In this study, the time-domain simulations have been performed for analysing the ship behaviour during berthing process with comparing the two different mathematical models for low and normal advance speed of a ship and the results have been presented. For the first step of programming, the traditional PD (Proportional Derivative) controller has been used for the control of speed and rudder and a tanker ship has been used as a simulation model. This study provides comparative results on the time-domain simulation of berthing operation of a ship for developing an effective simulation programme.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1066-1070
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• 2003

Recently technologies have created new principle and theory but the PID control system remains its popularity as the PID controller contains simple structure, including maintenance and parameter adjustment being so simple. Thus, this paper proposes auto tune PID by fuzzy logic controller based on FPGA which to achieve real time and small size circuit board. The digital PID controller design to consist of analog to digital converter which use chip TDA8763AM/3 (10 bit high-speed low power ADC), digital to analog converter which use two chip DAC08 (8 bit digital to analog converters) and fuzzy logic tune digital PID processor embedded on chip FPGA XC2S50-5tq-144. The digital PID processor was designed by fundamental PID equation which architectures including multiplier, adder, subtracter and some other logic gate. The fuzzy logic tune digital PID was designed by look up table (LUT) method which data storage into ROM refer from trial and error process. The digital PID processor verified behavior by the application program ModelSimXE. The result of simulation when input is units step and vary controller gain ($K_p$, $K_i$ and $K_d$) are similarity with theory of PID and maximum execution time is 150 ns/action at frequency are 30 MHz. The fuzzy logic tune digital PID controller based on FPGA was verified by control model of level control system which can control level into model are correctly and rapidly. Finally, this design use small size circuit board and very faster than computer and microcontroller.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.36 no.9
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• pp.1065-1071
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• 2012

Wind energy is becoming one of the most preferable alternatives to conventional sources of electric power that rely on fossil fuels. For stable electric power generation, constant rotating speed control of a wind turbine is performed through pitch control and stall control of the turbine blades. Recently, variable pitch control has been implemented in modern wind turbines to harvest more energy at variable wind speeds that are even lower than the rated one. Although wind turbine pitch controllers are currently optimized using a step response via the Ziegler-Nichols auto-tuning process, this approach does not satisfy the requirements of variable pitch control. In this study, the variable pitch controller was optimized by a genetic algorithm using a neural network model that was constructed by the Latin Hypercube sampling method to improve the Ziegler-Nichols auto-tuning process. The optimized solution shows that the root mean square error, rise time, and settle time are respectively improved by more than 7.64%, 15.8%, and 15.3% compared with the corresponding initial solutions obtained by the Ziegler-Nichols auto-tuning process.

• The Journal of the Korea Contents Association
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• v.21 no.1
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• pp.531-540
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• 2021

As cyber attacks and crimes increase exponentially and hacking attacks become more intelligent and advanced, hacking attack methods and routes are evolving unpredictably and in real time. In order to reinforce the enemy's responsiveness, this study aims to propose a method for developing an artificial intelligence-based security control platform by building a next-generation security system using artificial intelligence to respond by self-learning, monitoring abnormal signs and blocking attacks.The artificial intelligence-based security control platform should be developed as the basis for data collection, data analysis, next-generation security system operation, and security system management. Big data base and control system, data collection step through external threat information, data analysis step of pre-processing and formalizing the collected data to perform positive/false detection and abnormal behavior analysis through deep learning-based algorithm, and analyzed data Through the operation of a security system of prevention, control, response, analysis, and organic circulation structure, the next generation security system to increase the scope and speed of handling new threats and to reinforce the identification of normal and abnormal behaviors, and management of the security threat response system, Harmful IP management, detection policy management, security business legal system management. Through this, we are trying to find a way to comprehensively analyze vast amounts of data and to respond preemptively in a short time.