• Journal of the Korea Safety Management & Science
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• v.22 no.2
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• pp.7-13
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• 2020

Sludge incineration facilities are socially recognized as a hate facility. Therefore, a careful deodorization plan must be established. Therefore, the incineration facility must conduct research on odor ventilation. In this study, a odor diffusion simulation in an incineration facility was conducted and analyzed. In particular, research was carried out on carry-in rooms, pre-treatment rooms, and storage facilities for crops, which are expected to rapidly spread odor. As a result, ammonia 1.62, hydrogen sulfide 0.63, and acetaldehyde 0.73 were found in the transfer room. In addition, pretreatment rooms and stencil storage facilities were found to be lower than regulatory standards.

• Journal of computational fluids engineering
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• v.19 no.3
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• pp.52-61
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• 2014

The present paper deals with the efficient computation of higher-order CFD methods for compressible flow using graphics processing units (GPU). The higher-order CFD methods, such as discontinuous Galerkin (DG) methods and correction procedure via reconstruction (CPR) methods, can realize arbitrary higher-order accuracy with compact stencil on unstructured mesh. However, they require much more computational costs compared to the widely used finite volume methods (FVM). Graphics processing unit, consisting of hundreds or thousands small cores, is apt to massive parallel computations of compressible flow based on the higher-order CFD methods and can reduce computational time greatly. Higher-order multi-dimensional limiting process (MLP) is applied for the robust control of numerical oscillations around shock discontinuity and implemented efficiently on GPU. The program is written and optimized in CUDA library offered from NVIDIA. The whole algorithms are implemented to guarantee accurate and efficient computations for parallel programming on shared-memory model of GPU. The extensive numerical experiments validates that the GPU successfully accelerates computing compressible flow using higher-order method.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.32 no.3
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• pp.1-9
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• 2004

This study concentrates on the upwind schemes for convergence acceleration of the multigrid method for the Navier-Stokes equations. Comparative study of the upwind schemes in the Fourier space has been performed to identify why the second-order upwind scheme with enlarged stencil can be preconditioned better than the classical second-order upwind scheme. The full-coarsening multigrid method with implicit preconditioned multistage scheme has been implemented for verification of analysis. Numerical simulations on the inviscid and turbulent flows with the Spalart-Allmaras turbulent model have been performed. The results showed consistent trend with the analysis.

• Textile Coloration and Finishing
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• v.31 no.4
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• pp.233-240
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• 2019

Dyeing is an essential process for improving the value of textile products, but it is considered as one of industries causing pollution because of producing wastewater containing hazardous chemicals as well as using a large amount of water and energy. Global demand for greener technologies in textile field is getting much more attention and accordingly, the use of eco-friendly natural dyes is growing much larger. In textile printing, both dyes and pigments can be used. Pigment printing is more simple process and requires less water and less energy, compared to dye printing. In this study, the organic pigment was prepared from the marigold colorant. Samples were stencil printed, pressed(70℃, 3min) and then heat treated(150℃, 5min). The uptake of polyacrylic acid as a chemical binder was the lowest. In particular, marigold pigments were excellent in color and texture when Guar Gum and Sodium Alginate were used as binders. In addition, the light and washing fastness was rated very high as 4, 4/5 grades, and the rubbing fastness was also excellent as 3 and 4 grades.

• Progress in Superconductivity
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• v.12 no.2
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• pp.110-113
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• 2011

We have grown a Nb/Gd bilayer on a$SiO_2$/Si substrate by using a DC magnetron sputtering system, which was fabricated in situ with silicon stencil masks. In order to investigate proximity effect of the Nb/Gd bilayer, we used a planar tunnel junction with an AlOx tunnel barrier by oxidizing the Al ground electrode at the bottom. A $Co_{60}Fe_{40}$ backing of Al was deposited so as to reduce the superconductivity of the Al, ensuring a normal counterelectrode. With a 50-nm-thick Nb layer, we have measured dI/dV (dynamic conductance) by varying the thickness of Gd, which can reveal the density of states (DOS) of the Nb/Gd bilayer as a function of the Gd thickness resulting from the proximity effect of a superconductor/ferromagnet bilayer (S/F). The SF proximity effect in Nb/Gd will be discussed in comparison to our previous results of the CoFe/Nb, Ni/Nb and CuNi/Nb proximity effect; Gd is expected to show different effects since Gd has f-electrons, while CoFe, Ni, and CuNi have only d-electrons. Our studies will focus on the triplet correlation in a superconducting pair.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.2
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• pp.37-42
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• 2001

The BGA package has been the area array package of choice for several years. Recently, the transition has been to finer pitch configurations called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch. requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and place equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

• Journal of the Korean Society for Industrial and Applied Mathematics
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• v.24 no.1
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• pp.1-22
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• 2020

An accurate and efficient gradient estimation method on unstructured grid is presented by proposing a switching process between two Least-Square methods. Diverse test cases show that the gradient estimation by Least-Square methods exhibit better characteristics compared to Green-Gauss approach. Based on the investigation, switching between the two Least-Square methods, whose merit complements each other, is pursued. The condition number of the Least-Square matrix is adopted as the switching criterion, because it shows clear correlation with the gradient error, and it can be easily calculated from the geometric information of the grid. To illustrate switching process on general grid, condition number is analyzed using stencil vectors and trigonometric relations. Then, the threshold of switching criterion is established. Finally, the capability of Switching Weighted Least-Square method is demonstrated through various two- and three-dimensional applications.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.57-64
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• 2000

As integrated circuits become more complex, the number of I/O connections per chip grow. Conventional wire-bonding, lead-frame mounting techniques are unable to keep up. The space saved by shrinking die size is lost when the die is packaged in a huge device with hundreds of leads. The solution is bumps; gold, conductive adhesive, but most importantly solder bumps. Virtually every semiconductor manufacturer in the world is using or planning to use bump technology fur their larger and more complex devices. Several wafer-bumping processes used in the manufacture of bumped wafer. Some of the more popular techniques are evaporative, stencil or screen printing, electroplating, electrodes nickel, solder jetting, stud bumping, decal transfer, punch and die, solder injection or extrusion, tacky dot process and ball placement. This paper will discuss the process steps for bumping wafers using these techniques. Critical cleaning is a requirement for each of these processes. Key contaminants that require removal are photoresist and flux residue. Removal of these contaminants requires wet processes, which will not attack, wafer metallization or passivation. research has focused on enhanced cleaning solutions that meet this critical cleaning requirement. Process parameters defining time, temperature, solvency and impingement energy required to solvate and remove residues from bumped wafers will be presented herein.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.1
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• pp.51-59
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• 2000

As integrated circuits become more complex, the number of I/O connections per chip grow. Conventional wire-bonding, lead-frame mounting techniques are unable to keep up. The space saved by shrinking die size is lost when the die is packaged in a huge device with hundreds of leads. The solution is bumps; gold, conductive adhesive, but most importantly solder bumps. Virtually every semiconductor manufacturer in the world is using or planning to use bump technology for their larger and more complex devices. Several wafer-bumping processes used in the manufacture of bumped wafer. Some of the more popular techniques are evaporative, stencil or screen printing, electroplating, electroless nickel, solder jetting, stud humping, decal transfer, punch and die, solder injection or extrusion, tacky dot process and ball placement. This paper will discuss the process steps for bumping wafers using these techniques. Critical cleaning is a requirement for each of these processes. Key contaminants that require removal are photoresist and flux residue. Removal of these contaminants requires wet processes, which will not attack, wafer metallization or passivation. Research has focused on enhanced cleaning solutions that meet this critical cleaning requirement. Process parameters defining time, temperature, solvency and impingement energy required to solvate and remove residues from bumped wafers will be presented herein.

• 한국전산유체공학회:학술대회논문집
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• 2011.05a
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• pp.311-317
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• 2011

The present paper deals with the continuous works of extending the multi-dimensional limiting process (MLP) for compressible flows, which has been quite successful in finite volume methods, into discontinuous Galerkin (DG) methods. From the series of the previous, it was observed that the MLP shows several superior characteristics, such as an efficient controlling of multi-dimensional oscillations and accurate capturing of both discontinuous and continuous flow features. Mathematically, fundamental mechanism of oscillation-control in multiple dimensions has been established by satisfaction of the maximum principle. The MLP limiting strategy is extended into DG framework, which takes advantage of higher-order reconstruction within compact stencil, to capture detailed flow structures very accurately. At the present, it is observed that the proposed approach yields outstanding performances in resolving non-compressive as well as compressive flaw features. In the presentation, further numerical analyses and results are going to be presented to validate that the newly developed DG-MLP methods provide quite desirable performances in controlling numerical oscillations as well as capturing key flow features.