• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.1
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• pp.56-58
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• 2002

A closed form expression for the quality factor of the spiral inductor, methodologically, is presented as a function of the inductance ($L_{ind}$), metal-line width (W), spacing (S), inner and the diameter ($D_i$). For a given inductance, the dependences of quality factor on W, S, and $D_i$ are analyzed, and suggested the design optimization guidelines.

• ETRI Journal
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• v.28 no.1
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• pp.115-118
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• 2006

In this letter, a simple model parameter extraction methodology for an on-chip spiral inductor is proposed based on a wide-band inductor model that incorporates parallel inductance and resistance to model skin and proximity effects, and capacitance to model the decrease in series resistance above the frequency near the peak quality factor. The wide-band inductor model does not require any frequency dependent elements, and model parameters can be extracted directly from the measured data with some curve fitting. The validity of the proposed model and parameter extraction methodology are verified with various size inductors fabricated using $0.18\;{\mu}m$ CMOS technology.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.796-800
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• 2004

The main research on this paper is to model on-chip inductor in digital CMOS technology by using the foundry parameters and the physical structure. The s-parameters of a spiral inductor are extracted from the modeled equivalent circuit and then compared to the results obtained from HFSS. The structure and material of the inductor used for modeling in this work is identical with those of the inductor fabricated by CMOS process. To show why the modeled inductor instead of ideal inductor should be used to design a RF system, we designed dual band RF front-end receiver and then compared the results between when using the ideal inductor and using the modeled inductor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.10
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• pp.11-16
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• 2000

The SPICE model of the spiral inductor on silicon substrate which can be easily used for the RF IC design has been developed. In this proposed model the equivalent circuit element of the spiral inductor are defined by the layout and process parameters using the user-defined function and subcircuit of the SPICE. The total inductance is calculated using the subcircuit Li for the arbitrary turn i and the subcircuit Mij for two arbitrary turns. The model was verified by comparing the simulated data with the measured s-parameters, total inductance, and quality factor of the spiral inductor fabricated by the CMOS 0.8${\mu}m$ process. The proposed SPICE model of the spiral inductor is scalable and includes the effects of the silicon substrate.

• Proceedings of the KIEE Conference
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• 2003.04a
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• pp.289-291
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• 2003

This paper deals with the design of a spiral micro inductor using LTCC(Low Temperature Cofired Ceramics) technology. The inductors using the LTCC technology have some prominent properties of high integration of circuits, high confidence and low cost comparing with previously fabricated thick-film inductors. In this paper, we designed a new spiral-type micro inductor comprising a magnetic material to improve the inductance and leakage flux. we, in addition, presented the simulation results for various shapes of the magnetic material in the micro inductor, Finally application of the micro inductor to the boost DC-DC converter is investigated.

• Journal of electromagnetic engineering and science
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• v.8 no.2
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• pp.47-51
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• 2008

In this paper, we present a cost effective parallel-branch spiral inductor with the enhanced quality factor and the resonance frequency. This structure is designed to improve the quality factor, but different from other fully stacked spiral inductors. The parallel-branch effect is increased by overlapping the first metal below the second metal with same direction. Measurement result shows an increased quality factor of 12 % improvement. Also, we show an octagonal parallel-branch inductor which reduces the parasitic capacitances for higher frequency applications.

• 한국정보통신설비학회:학술대회논문집
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• 2007.08a
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• pp.436-439
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• 2007

This paper describes the optimization of PGS(Patterned Ground Shield) of 5.5 turns rectangular spiral inductor using Taguchi's method. PGS is decrease method of parasite component by silicon substrate among dielectric loss reduction method. By using the taguchi's method, each parameter is fixed upon that PGS high poison(A), slot spacing(B), strip width(C) and overlap turn number(D) of PGS design parameter. Then we verified that percentage contribution and design sensitivity analysis of each parameter and level by signal to noise ratio of larger-the-better type. We consider percentage contribution and design sensitivity of each parameter and level, and then verify that model of optimization for PGS is lower inductance decreasing ratio and higher Q-factor increasing ratio by EM simulation.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.283-286
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• 1999

A 2㎓, low noise, low power CMOS voltage-controlled oscillator (VCO) with an integrated LC resonator is presented. The design of VCO relies heavily on the on-chip spiral inductor. An optimized spiral inductor with Q-factor of nearly 8 is achieved and used for the VCO. The simulated result of phase noise is as low as -l14 ㏈c/Hz at an offset frequency of a 600KHz from a 2㎓ carrier frequency. The VCO is tuned with standard available junction capacitors, resulting in an about 400MHz tuning range (20%). Implemented in a five-metal 0.25${\mu}{\textrm}{m}$ standard CMOS process, the VCO consumes only 2㎽ from a single 2.5V supply. It occupies an active area of 620${\mu}{\textrm}{m}$$\times$720${\mu}{\textrm}{m}$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.1
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• pp.83-87
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• 2003

In the present paper we suggested a parallel branch structure of aluminum spiral inductor for the use of RF integrated circuit at 1∼3 GHz. The inductor was implemented on p-type silicon wafer (5∼15Ω-cm) under the standard CMOS process and it showed a enhanced qualify(Q) factor by more than 10 % with no degradation of inductance. The effect of the structure modification on the Q factor and the inductance was scrutinized comparing with conventional spital inductors

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.987-990
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• 2003

This paper presents a cross-coupled RF VCO with high-Q MEMS-based spiral inductors. Since the use of high-Q inductors is critical to VCO design, MEMS-based spiral inductors with the Q-factor of nearly 22 are used for the RF VCO with an active cascode current source. The RF VCO circuits including spiral inductors have been designed and simulated in GaAs MMIC-MEMS process. The simulation results of the VCO circuits showed the phase noise of -180dBc/Hz at an offset frequency of 500KHz. The RF VCO circuit simulatinon used 2mA DC current and 3.3V supply.