• Title/Summary/Keyword: Speed Detector

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An Adaptive Partial Response Equalizer Using Branch Metrics of Viterbi Trellis for Optical Recording Systems (고밀도 광 기록 장치에서 비터비 트렐리스의 가지 메트릭을 이용한 부분 응답 적응 등화기)

  • Lee, Kyu-Suk;Lee, Joo-Hyun;Lee, Jae-Jin
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.9C
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    • pp.871-876
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    • 2005
  • In this paper, we propose an improved partial response maximum likelihood (PRML) detection scheme that has an adaptive equalizer and can be applied in the asymmetric optical recording system with high-density. We confirmed that the proposed PRML detector improves detection performance. In addition, we implemented the detector by Verilog HDL. The adaptive equalizer is composed of tap coefficient updating unit using LMS algorithn and FIR filter. FIR filter is implemented by the transposed direct form architecture for high speed operation. Viterbi detector is implemented by the register exchange method.

Research for realization of platform of portable radiation detector using NaI(Tl) Scintillator (NaI(Tl) Scintillator를 이용한 휴대용 방사선 검출 장치 구현에 대한 연구)

  • Lee, Jon-Hwey;Joh, Yool-Hee;Lee, Yoon-Ho;Lim, Ik-Chan;Kim, Young-Kil
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.10
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    • pp.2323-2328
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    • 2012
  • Over the world, the development of critical technology for the safety and security of coastal distribution based on ubiquitous computing is being processed to meet the bottom lines of governmental regulations. Currently, 3D detectors using X-rays for freight search technology are being developed concerning U-based shipping security systems. In addition to that, there are increasing needs for developing portable radiation detector to detect gamma rays. The purpose of the thesis is to suggest the research of high speed portable gamma rays detector platform to prevent disorder caused to humans and public objects.

Design of a 2.5 Gb/s Clock and Data Recovery Circuit (2.5 Gb/s 클럭 및 데이터 복원 회로의 설계)

  • Lee, Young-Mi;Woo, Dong-Sik;Lee, Ju-Sang;Kim, Kang-Wook;Yu, Sang-Dae
    • Proceedings of the KIEE Conference
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    • 2002.11c
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    • pp.593-596
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    • 2002
  • A design of clock and data recovery (CDR) circuit for the SONET OC-48 using a standard 0.18 ${\mu}m$ CMOS process has been performed. The phase detector and the charge pump must be able to operate at the 2.5 Gb/s input data speed and also accurately compare phase errors to reduce clock jitter. As a phase detector, the Hogge phase detector is selected but two transistors are added to improve the performance of the D-F/F. The charge pump was also designed to be placed indirectly input and output. A general ring oscillator topology is presented and simulated. It provides five-phase outputs and 220 MHz to 3.12 GHz tuning range.

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Study on NMR Measurment of Flowing Water by a Separated Detector (분리형 감지기를 이용한 흐르는 물의 핵자기공명 측정연구)

  • ;;;;V. Ya. Shifrin
    • Journal of the Korean Magnetics Society
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    • v.5 no.3
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    • pp.165-170
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    • 1995
  • NMR measurement has been studied for protons in pre-polarized flowing water by a separated detector working at high field far away from the measured field region where the transition of protons is occurred by the pertur-bation of RF energy. The conditions for NMR signal were optimized on the amplitude and frequency of modulation field, the RF field of detector, water speed, and RF field at the measured field region. The NMR signal with the full width of 320 nT at the half maximum in Lorentzian curve and with signal to noise ratio of 10.5 was measured in the range from a few ${\mu}T$ to mT, and its shape and amplitude were independent of the measured field intensity and its uniformity.

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Multi-Task FaceBoxes: A Lightweight Face Detector Based on Channel Attention and Context Information

  • Qi, Shuaihui;Yang, Jungang;Song, Xiaofeng;Jiang, Chen
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.14 no.10
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    • pp.4080-4097
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    • 2020
  • In recent years, convolutional neural network (CNN) has become the primary method for face detection. But its shortcomings are obvious, such as expensive calculation, heavy model, etc. This makes CNN difficult to use on the mobile devices which have limited computing and storage capabilities. Therefore, the design of lightweight CNN for face detection is becoming more and more important with the popularity of smartphones and mobile Internet. Based on the CPU real-time face detector FaceBoxes, we propose a multi-task lightweight face detector, which has low computing cost and higher detection precision. First, to improve the detection capability, the squeeze and excitation modules are used to extract attention between channels. Then, the textual and semantic information are extracted by shallow networks and deep networks respectively to get rich features. Finally, the landmark detection module is used to improve the detection performance for small faces and provide landmark data for face alignment. Experiments on AFW, FDDB, PASCAL, and WIDER FACE datasets show that our algorithm has achieved significant improvement in the mean average precision. Especially, on the WIDER FACE hard validation set, our algorithm outperforms the mean average precision of FaceBoxes by 7.2%. For VGA-resolution images, the running speed of our algorithm can reach 23FPS on a CPU device.

A CMOS 5.4/3.24-Gbps Dual-Rate CDR with Enhanced Quarter-Rate Linear Phase Detector

  • Yoo, Jae-Wook;Kim, Tae-Ho;Kim, Dong-Kyun;Kang, Jin-Ku
    • ETRI Journal
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    • v.33 no.5
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    • pp.752-758
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    • 2011
  • This paper presents a clock and data recovery circuit that supports dual data rates of 5.4 Gbps and 3.24 Gbps for DisplayPort v1.2 sink device. A quarter-rate linear phase detector (PD) is used in order to mitigate high speed circuit design effort. The proposed linear PD results in better jitter performance by increasing up and down pulse widths of the PD and removes dead-zone problem of charge pump circuit. A voltage-controlled oscillator is designed with a 'Mode' switching control for frequency selection. The measured RMS jitter of recovered clock signal is 2.92 ps, and the peak-to-peak jitter is 24.89 ps under $2^{31}-1$ bit-long pseudo-random bit sequence at the bitrate of 5.4 Gbps. The chip area is 1.0 mm${\times}$1.3 mm, and the power consumption is 117 mW from a 1.8 V supply using 0.18 ${\mu}m$ CMOS process.

Giga-bps CMOS Clock and Data Recovery Circuit with a novel Adaptive Phase Detector (새로운 구조의 적응형 위상 검출기를 갖는 Gbps급 CMOS 클럭/데이타 복원 회로)

  • 이재욱;이천오;최우영
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.10C
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    • pp.987-992
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    • 2002
  • In this paper, a new clock and data recovery circuit is proposed for the application of data communication systems requiring ㎓-range clock signals. The circuit is suitable for recovering NRZ data which is widely used for high speed data transmission in ㎓ ranges. The high frequency jitter is one of major performance-limiting factors in PLL, particularly when NRZ data patterns are used. A novel phase detector is able to suppress this noise, and stable clock generation is achieved. Futhermore, the phase detector has an adaptive delay cell removing the dead zone problem and has the optimal characteristics for fast locking. The proposed circuit has a convenience structure that can be easily extended to multi-channels. The circuit is designed based on CMOS 0.25㎛ fabrication process and verified by measurement result.

Development of an Arc Detector Assessment System by Loss of Contact Between Pantograph and Contact Wire in Electric Railway (전기철도 팬터그래프-전차선간 이선아크 검측 평가 기술 개발)

  • Park, Young;Cho, Yong-Hyeon;Kwon, Sam-Young;Lee, Ki-Won;You, Won-Hee
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.60 no.11
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    • pp.2171-2175
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    • 2011
  • The objective of this paper is to discuss technologies on assessing reliability of arc detectors by composing a system that generates and simulates occurrence of arc caused by loss of contact between pantographs and contact wires in a laboratory condition. In order to establish the arc simulator, a device that generates light having the bandwidth of arcs that occur between carbon-metal. The simulator was designed under conditions of EN 50317 and simulations were conducted using the developed device. According to the results, it was possible to conduct certification tests following regulations of international standards and the precision of the simulator was satisfactory. The proposed arc detector assessment system is expected to enhance precision of current collection quality performance assessment methods at high-speed lines and conventional lines while being referred as fundamental technologies for development of detectors suiting international conditions.

Development of Radiation Thermometer using InSb Photo-detector (인듐안티모나이드(InSb) 소자를 이용한 적외선 방사온도 계측시스템의 개발연구)

  • Hwang, Byeong-Oc;Lee, Won-Sik;Jhang, Kyung-Young
    • Journal of the Korean Society for Precision Engineering
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    • v.12 no.7
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    • pp.46-52
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    • 1995
  • This paper proposes methodologies for the development of radiation thermometer using InSb photo-detector of which spectral sensitivity is excellent over the wave length range of 2 .mu. m .approx. 5 .mu. m. The proposed radiation thermometer has broad measurement range from normal to high, up to more than 1000 .deg. C, with high accuracy, and can measure temperature on the material surface or heat emission noncontactely with high speed. Optical system was consisted of two convex lens with foruslength of 15.2mm for infrared lay focusing, Ge filter to cut the short wave length components and sapphire filter to cut the long wave length components. The cold shielded was installed in the whole surface of the light-absorbing element to remove the error- mometer, calibration using black body furnace which has temperature range of 90 .deg. C .approx. 1100 .deg. C was carried out, and temperature calaibration curve was obtained by exponential function curvefitting. The result shows maximum error less than 0.24%(640K .+-. 1.6K) over the measurement range of 90 .deg. C .approx. 700 .deg. C, and from this result the usefulness of the developed thermometer has been confirmed.

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The Extreme Low Speed Motor Observer and Brake Torque Control Technologies (극 저속 전동기용 관측기 및 제동 토크 제어 기술)

  • Kim, Young-Choon
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.14 no.1
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    • pp.363-368
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    • 2013
  • This paper relates to the electric braking, the permanent magnet synchronous motor vector control is suspended until the applied, and propose a new scheme by the controller in the observer to estimate the position and velocity using the Resolver speed detector. In addition, as a way to control the speed by braking torque at low speed, the pole of a stop just before the stop electrical braking. As a result, noise and dust abatement, consumption, reduction of the brake shoe increase the maintainability of comfort and energy use, enhances the effect of EMU performance improved sikyeoteum could see.