• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.1
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• pp.96-102
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• 1995

This paper presents the VHSIC Hardware Description Language(VHDL) implementation of the Fixed Point Covariance Lattice(FLAT) algorithm for an Linear Predictive Coding(LPC) analysis and its related algorithms, such as the forth order high pass Infinite Impulse Response(IIR) filter, covariance matrix calculation, and Spectral Smoothing Technique(SST) in the Vector Sum Exited Linear Predictive(VSELP) speech coder that has been Selected as the standard speech coder for the North America and Japanese digital cellular. Existing Digital Signal Processor(DSP) chips used in digital cellular phones are derived from general purpose DSP chips, and thus, these DSP chips may not be optimal and effective architectures are to be designed for the above mentioned algorithms. Then we implemented the VHDL code based on the C code, Finally, we verified that VHDL results are the same as C code results for real speech data. The implemented VHDL code can be used for performing logic synthesis and for designing an LPC Application Specific Integrated Circuit(ASOC) chip and DsP chips. We first developed the C language code to investigate the correctness of algorithms and to compare C code results with VHDL code results block by block.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.1 no.1
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• pp.77-83
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• 1997

In this paper, we present a comparison between QCELP(Qualcomm Code Excited Linear Predictor) speech coder that is operating in digital mobile communication system and CS-ACELP(Conjugate Structure Algebraic Code Excited Linear Prediction) speech coder that is scheduled to use for IMT-2000 (International Mobile Telecommunications 2000) system. The performance comparison might give help to design of the speech coding algorithms so that the robustness of the algorithms to channel errors engaged by mobile communication system be optimized.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.273-276
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• 2000

Recently, Turbo code has been considered for channel coding in IMT-2000(International Mobile Telecommunication-2000) system, because it offers better error correcting capability than the traditional convolution/viterbi coding . In this paper, a turbo code decoder for speech transmission in IMT-2000 system with frame size 192 bits, constrait length K=3, generator polynomials G(5,7) and code rate R=1/3 is designed using SOVA(Soft Output Viterbi Algorithm) and block interleaver

• Speech Sciences
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• v.11 no.2
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• pp.259-269
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• 2004

In this paper, we propose a new excitation enhancement technique to improve the speech quality of low bit-rate code-excited linear prediction (CELP) coders. The proposed technique is based on a harmonic model and it is employed only in the decoding process of speech coders without any additional bits. We develop the procedure of harmonic model parameter estimation and harmonic generation, and apply this technique to a current state-of-the-art low bit rate speech coder, ITU-T G.729 Annex D. Also, its performance is measured by using the ITU-T P.862 PESQ score and compared to those of the phase dispersion filter and the long-term postfilter applied to the decoded excitation. It is shown that the proposed excitation enhancement technique can improve the quality of decoded speech and provide better quality for male speech than other techniques.

• Proceedings of the IEEK Conference
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• 2000.06d
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• pp.92-97
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• 2000

An AMR(Adaptive Multi-Rate) speech coding algorithm has been adopted as a standard speech codec for IMT-2000. It is based on the algebraic CELP, and consists of eight speech coding modes having the bit rate from 4.75 kbit/s to 12.2 kbit/s. It also contains the VAD(Voice Activity Detector), SCR (Source Controlled Rate) operation, and error concealment scheme for robustness in a radio channel. The bit rate of AMR is changed on a frame basis depending on the channel condition. In this paper, we introduced AMR speech coding algorithm and performed the real-time implementation using TMS320C6201, i.e., a Texas Instrument's fixed-point DSP. With the ANSI C source code released from ETSI and 3GPP, we convert and optimize the program to make it run in real time using the C compiler and assembly language. It is verified that the decoded result of the implemented speech codec on the DSP is identical with the PC simulation result using ANSI C code for test sequences. Also, actual sound input/output test using microphone and speaker demonstrates its proper real-time operation without distortions or delays.

• Speech Sciences
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• v.10 no.2
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• pp.65-75
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• 2003

This paper describes the issues associated with the real-time implementation of G.723.1A dual-rate speech coder on a TMS320VC5402 DSP. Firstly, the main features of the G.723.1A speech coder and the procedure involved in the implementation using assembly and C languages are discussed. Various real-time implementation issues such as memory/MIPS tradeoffs are also presented. For fixed-point implementation, we converted the ITU-T fixed-point ANSI C code into TMS320VC5402 code in the bit-exact way through verification using the test vectors. Finally, as the result of implementation, we present the MIPS and memory requirement for the real-time operation.

• ETRI Journal
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• v.19 no.3
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• pp.242-258
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• 1997

The Qualcomm code excited linear prediction (QCELP) speech coder was adopted to increase the capacity of the CDMA Mobile System (CMS). In this paper, we implemented the QCELP speech coding algorithm by using TMS320C50 fixed point DSP chip. Also the fixed point simulation was done with C language. The computation complexity of QCELP on TMS320C50 was 10k words and data memory was 4k words. In the normal call test on the CMS, where mobile to mobile call test was done in the bypass mode without double vocoding, mean opinion score for the speech quality was he Qualcomm code excited linear prediction (QCELP) speech quality was 3.11.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.490-492
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• 2018

This paper presents an analysis of the AMR speech data as a basic work to study the technique of inputting and transmitting AMR voice data which is widely used in the public cell phone. AMR consists of HEADER and Speech Data, and it is transmitted in bit format and has 8 bit-rate modes in total. HEADER contains mode information of Speech Data, and the length of Speech Data differs depending on the mode. We chose the best mode which is best to input into QR code and analyzed that mode. It is a goal to show a higher compression ratio for voice data by the analysis and experiments. This analysis shows improvement in that it can transmit voice data more effectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.2C
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• pp.167-172
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• 2008

Since a 2-dimensional (2D) bar code can retrieve data and information quickly, it is widely used and recognized as a useful tool for many industrial applications. However, the information capacity of the 2D bar code is still limited. Recently the analog-digital code (AD code), which has the largest storage capacity yet contained in a code, has been developed, thereby expanding the bar code's application range because it overcomes the limitation of data capacity. In this paper, we present the AD code and implement an effective embedded system which can transform text information into voice using the 2D AD code and Text To Speech (TTS). This voice information can also be transmitted to blind people as well as the old by capturing the AD code on paper or in books.

• The Journal of the Acoustical Society of Korea
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• v.18 no.5
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• pp.44-51
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• 1999

This paper presents a massively parallel computational model for the efficient integration of speech and natural language understanding. The phoneme model is based on continuous Hidden Markov Model with context dependent phonemes, and the language model is based on a knowledge base approach. To construct the knowledge base, we adopt a hierarchically-structured semantic network and a memory-based parsing technique that employs parallel marker-passing as an inference mechanism. Our parallel speech recognition algorithm is implemented in a multi-Transputer system using distributed-memory MIMD multiprocessors. Experimental results show that the parallel speech recognition system performs better in recognition accuracy than a word network-based speech recognition system. The recognition accuracy is further improved by applying code-phoneme statistics. Besides, speedup experiments demonstrate the possibility of constructing a realtime parallel speech recognition system.