• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.9
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• pp.2022-2028
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• 2015

SpaceWire is a standard for high-speed links and networks between spacecraft components, which was invented for better, cheaper and faster on-board data handling in spacecraft. The standard defines timecode and its distribution which can be used for time synchronization among the nodes in a SpaceWire network. A timecode output from the time master which provides standard time over a SpaceWire network travels through links and routers to reach every nodes. While traveling, a timecode suffers from transmission delay and jitter which cause some difference in time synchronization among nodes. In this work, a simulator was developed using OMNeT++ to simulate the operation of a SpaceWire network and some analyses were performed on the transmission delay and jitter accompanied with a transmission of a timecode. The result will be used in the near future for the research of a precise time synchronization technique over a SpaceWire network.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.724-730
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• 2017

SpaceWire invented for spacecrafts has Time-Code defined for time synchronization over SpaceWire network. A Time-Code suffers transmission delay of 14[bit-period] and jitter up to 10[bit-period] whenever it passes through a SpaceWire link, which is the primary cause of time synchronization error. This work presents a simple method to improve the time synchronization which uses two extended Time-Codes. Nodes on a SpaceWire network can find how much delay and jitter a received Time-Code has suffered while it passes through the network, and they can correct time synchronization error with this information. The proposed method was validated in a simulation environment developed based on OMNeT++. The simulation result showed that time synchronization error less than a few bit-periods can be achieved. The proposed method is cost effective and suitable for small-scale SpaceWire network systems.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.715-718
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• 2016

SpaceWire invented for on-board data handling in a spacecraft has Time-Code defined for time synchronization over SpaceWire network. Delay and jitter of the transmission of Time-Code caused when a Time-Code travels through a network are the main reasons of time synchronization error. This work proposes a scheme that can reduce the time synchronization error by using extended Time-Codes. The proposed scheme can remove both transmission jitter and transmission delay. The scheme will be validated in a simulation environment built with OMNeT++.

• Bulletin of the Korean Space Science Society
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• 2007.10a
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• pp.87-87
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• 2007

• Aerospace Engineering and Technology
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• v.4 no.2
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• pp.79-87
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• 2005

This paper describes a new on-board computer design for the next generation satellite. The new on-board computer utilizes centralized processing architecture with MCMERC325C CPU based on functional modular design concepts. The on-board computer consists of PM32 Module, TC-TM Module, IO Module and Power module. The IEEE-1355 DS/DE, or SpaceWire, provides a standard communication interface between module. It also provides simple cross-strap design for redundancy management and increases re-usability of the modules.

• Journal of Satellite, Information and Communications
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• v.11 no.3
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• pp.65-71
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• 2016

Currently developing the OBC of the next-generation LEO satellite by Korea Aerospace Research Institute adopts the LEON2-FT/AT697F processor to achieve high performance. And various communication devices such as SpaceWire, MIL-STD-1553B, DMAUART and CAN Master are integrated to the separated standard communication FPGAs within the OBC, where they can be controlled by the processor and flight software (FSW) through PCI interface. The Actel 1553BRM IP core is used for the 1553B in the next-generation LEO OBC and the B1553BRM wrapper from Aeroflex Gaisler is used for connecting it to the AMBA bus in FPGA. This paper presents the design and development of PCI-based 1553B communication software, and describes the handling mechanism of 1553B operation in FSW task level. Also it shows the test results on real-hardware and simulator.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.4
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• pp.35-41
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• 2020

The small tracking radar is a very important component of the wire harness design because the components are organically connected. In addition, the cable connected to the signal processing unit and the servo unit having a large number of digital signals should be prepared to prevent the CPU of the signal processing unit from malfunctioning due to electromagnetic noise. Cables for signal transmission in the ◯◯ GHz band must reflect the design of temperature, vibration, and shock. To design a wire harness in a small space, the size of the connector must be minimized. The issues to be considered are described and the design plan is presented.

• Aerospace Engineering and Technology
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• v.13 no.2
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• pp.38-46
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• 2014

CRC (Cyclic Redundancy Codes) is a error detection method for the date transmission, which is applied to the GRDDP (GOES-R Reliable Data Delivery Protocol) between satellite and GEMS (Geostationary Environmental Monitoring Sensor) on the GEO-KOMPSAT 2B development. This paper introduces a principle of the table based CRC, and explains software implementation results of the CRC8 applied to GEMS.

• Journal of Satellite, Information and Communications
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• v.8 no.1
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• pp.54-60
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• 2013

The need for high performance of on-board computer (OBC) is essential due to the growing requirements and diversified missions, and so OBC has been developed on the basis of the standard design and reconfigurable modularization in order to improve the utilization of OBC for different missions. The processor in OBC of next generation satellite which is currently developed by KARI is adopted the LEON2-FT/AT697F processor based SPARC v8 as main processor and controls various devices such as SpaceWire, MIL-STD-1553B and CAN through PCI on the standardized communication chips. This paper presents the architecture and design of system software for LEON2-FT processor based on PCI, and development of PCI software component. Also it describes the porting of VxWorks 6.5 for LEON2-FT and the test under the simulation environment for LEON2-FT and PCI with communication chips.

• The Bulletin of The Korean Astronomical Society
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• v.37 no.2
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• pp.184.2-184.2
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• 2012

위성의 전장품은 전기적 접속을 위해서 1:1 연결을 하는 Point-to-Point 버스 방식과 여러개의 Slave (Remote Terminal)을 갖고, 일반적으로 1개의 Master (Controller)에 의해서 연결하게 되는 버스 구조를 갖는 접속 채널을 통해서 연결이 된다. 가장 많이 사용되는 방식인 MIL-STD-1553B는 데이터 전송속도가 1Mbps이고, Transformer에 의해서 완전하게 버스와 각 전장품이 완전하게 절연이 되는 구조로, 전기적 고장이 전달되는 것을 방지할 수가 있지만, 설계의 난이도가 높다. 고속 버스는 SpaceWire를 사용하고, 100Mbps이상의 속도를 지원할 수가 있지만, LVDS등의 고속 채널 설계 및 노이즈에 민감한 특성 때문에, 저속의 통신채널에서는 사용하기 어렵다. 저속의 데이터 채널을 위해서는 UART 방식이 사용된다. UART 방식은 RS-422 방식과 RS-485 방식이 사용되지만, 1553B 또는 SpaceWire 등과 같이 프로토콜이 정해지지 않아서, 사용자가 직접 프로토콜을 지정해야하는 문제가 있다. 또한 RS-422은 1:1 방식의 Point-to-Point UART를 위해서 사용되고, RS-485는 버스 방식의 연결을 지원할 수가 있지만, 동시에 여러개의 TX가 enable되는 경우에는 TX사이에 고장을 일으킬 수 있어서, 1번에 TX가 1개만 사용되도록 제어할 필요가 있다. 또한 RS-485방식의 버스를 구현할 경우에는 1553B처럼 와전하게 절연이 불가능하므로, 전기적이나 기능적으로 485버스에 문제가 발생할 경우에 절연과 같은 기능이 지원되도록 구현이 되어야 한다. 본 논문에서는 안정적인 485 UART버스 구현을 위한 기술에 대해서 평가하고 분석하도록 하겠다.