• 대한전기학회논문지
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• 제36권7호
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• pp.462-469
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• 1987

A metal gate MOSFET with source/drain regions self-aligned to gate region is proposed. The proposed MOS transistor is fabricated by utilizing the higher oxidation rate of source/drain regions with high doping concentration when compared with channel region with moderate doping. The thick oxide on the source/drain regions reduces the gate and drain(source) overlap capacitance down to that of a self-aligned polysilicon gate device while allowing the use of a metal gate with much lower resistivity than the more commonly used polycrystalline silicon. A ring oscillator composed of 15 inverter stages has been computer simulated using SPICE. The results of the simulation show good agreement with experimental measurement confirming the fast switching speed of propesed MOSFET.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권6호
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• pp.576-580
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• 2013

We investigate the enhanced effects of asymmetry ratio variations of the source and drain area in silicon (Si) field-effect transistor (FET). Photoresponse according to the variation of asymmetry difference between the width of source and drain are obtained by using the plasmonic terahertz (THz) wave detector simulation based on technology computer-aided design (TCAD) with the quasi-plasma 2DEG model. The simulation results demonstrate the potential of Si FETs with asymmetric source and drain structures as the promising plasmonic THz detectors.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2012년도 춘계학술발표대회
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• pp.110.2-110.2
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• 2012

We reported on antireflective ZnSnO (ZTO)/Ag bilayer and ZTO/Ag/ZTO trilayer source/drain (S/D) electrodes for all-transparent ZTO channel based thin film transistors (TFTs). The ZTO/Ag bilayer is more transparent (83.71%) and effective source/drain (S/D) electrodes for the ZTO channel/Al2O3 gate dielectric/ITO gate electrode/glass structure than ZTO/Ag/ZTO trilayer because the bottom ZTO layer in the trilayer increasea contact resistance between S/D electrodes and ZTO channel layer and reduce the antireflection effect. The ZTO based all-transparent TFTs with ZTO/Ag bilayer S/D electrode showed a saturation mobility of 4.54cm2/Vs and switching property (1.31V/decade) comparable to TTFT with Ag S/D electrodes.

• E2M - 전기 전자와 첨단 소재
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• 제8권5호
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• pp.626-632
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• 1995

In this paper, The effect of the impedances in SNOSFET's memory devices has been developed. The effect of source and drain impedances measured by means of two bias resistances - field effect bias resistance by inner region, external bias resistance. The effect of the impedances by source and drain resistance shows the dependence of the function of voltages applied to the gate. It shows the differences of change in source drain voltage by means of low conductance state and high conductance state. It shows the delay of threshold voltages. The delay time of low conductance state and high conductance state by the impedances effect shows 3[.mu.sec] and 1[.mu.sec] respectively.

• Transactions on Electrical and Electronic Materials
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• 제12권6호
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• pp.271-274
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• 2011

Screen-printed source and drain electrodes were used for a spin-coated and inkjet-processed zinc-tin oxide (ZTO) TFTs for the first time. Source and drain were silver nanoparticles. Channel length was patterned using screen printing technology. Different silver nanoinks and process parameters were tested to find optimal source and drain contacts Relatively good electrical properties of a screen-printed inkjet-processed oxide TFT were obtained as follows; a mobility of 1.20 $cm^2$/Vs, an on-off current ratio of $10^6$, a Vth of 5.4 V and a subthreshold swing of 1.5 V/dec.

• Journal of information and communication convergence engineering
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• 제5권1호
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• pp.42-44
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• 2007

The a-Si:H TFTs decreasing parasitic capacitance of source-drain is fabricated on glass. The structure of a-Si:H TFTs is inverted staggered. The gate electrode is formed by patterning with length of $8{\mu}m{\sim}16{\mu}m$ and width of $80{\sim}200{\mu}m$ after depositing with gate electrode (Cr) $1500{\AA}$ under coming 7059 glass substrate. We have fabricated a-SiN:H, conductor, etch-stopper and photoresistor on gate electrode in sequence, respectively. The thickness of these, thin films is formed with a-SiN:H ($2000{\mu}m$), a-Si:H($2000{\mu}m$) and $n^+a-Si:H$ ($500{\mu}m$). We have deposited $n^+a-Si:H$, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the $n^+a-Si:H$ layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si:H TFTs decreasing parasitic capacitance of source-drain show drain current of $8{\mu}A$ at 20 gate voltages, $I_{on}/I_{off}$ ratio of ${\sim}10^8$ and $V_{th}$ of 4 volts.

• 한국정보통신학회논문지
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• 제20권4호
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• pp.793-798
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• 2016

본 연구에서는 1T-DRAM 응용을 위해 Bipolar Junction Transistor 모드 (BJT mode)에서 비대칭 소스/드레인 수직형 나노와이어 소자의 순방향 및 역방향 메모리 윈도우 특성을 분석하였다. 사용된 소자는 드레인 농도가 소스 농도보다 높으며 소스 면적이 드레인 면적보다 큰 사다리꼴의 수직형 gate-all-around (GAA) MOSFET 이다. BJT모드의 순방향 및 역방향 이력곡선 특성으로부터 순방향의 메모리 윈도우는 1.08V이고 역방향의 메모리 윈도우는 0.16V이었다. 또 래치-업 포인트는 순방향이 역방향보다 0.34V 큰 것을 알 수 있었다. 측정 결과를 검증하기 위해 소자 시뮬레이션을 수행하였으며 시뮬레이션 결과는 측정 결과와 일치하는 것을 알 수 있었다. 1T-DRAM에서 BJT 모드를 이용하여 쓰기 동작을 할 때는 드레인 농도가 높은 것이 바람직함을 알 수 있었다.

• 한국정보통신학회논문지
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• 제8권4호
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• pp.821-825
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• 2004

본 연구는 에치스토퍼를 기존의 방식과 다르게 적용하여 수소화 된 비정질 실리콘 박막 트랜지스터의 제조공정을 단순화하고, 박막 트랜지스터의 게이트와 소오스-드레인간의 기생용량을 줄인다. 본 연구의 수소화 된 비정질 실리콘 박막 트랜지스터는 Inverted Staggered 형태로 게이트 전극이 하부에 있다. 실험 방법은 게이트전극, 절연층 , 전도층, 에치스토퍼 및 포토레지스터층을 연속 증착한다. 스토퍼층을 게이트 전극의 패턴으로 남기고, 그 위에 n+a-Si：H 층 및 NPR(Negative Photo Resister)을 형성시킨다. 상부 게이트 전극과 반대의 패턴으로 NPR층을 패터닝하여 그것을 마스크로 상부 n+a-Si：H 층을 식각하고, 남아있는 NPR층을 제거한다. 그 위에 Cr층을 증착한 후 패터닝하여 소오스-드레인 전극을 위한 Cr층을 형성시켜 박막 트랜지스터를 제조한다. 이렇게 제조하면 기존의 박막 트랜지스터에 비하여 특성은 같고, 제조공정은 줄어들며, 또한 게이트와 소오스-드레인간의 기생용량이 줄어들어 동작속도를 개선시킬 수 있다.

• 대한전자공학회논문지
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• 제27권6호
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• pp.895-900
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• 1990

With the MOS device scailing down, the substrate concentration must increase in order to avoid punchthrough leakage current due to the DIBL(Drain Induced Barrier Lowering) effect. However the enhancement of the substrate concentration increases source, drain juntion capacitances and substrate current due to hot elelctron, degrading the speed characteristics and reliability of the MOS devices. In this paper, a new device, called CODE(Channel Only Dopant Enhancement) MOS, an its fabrication are proposed. By comparing the fabricated CODE MOSFET with the conventional device, the improvements on DIBL, substrate current and source, drain juntion capacitances are realized.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2010년도 춘계학술대회 논문집
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• pp.693-694
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• 2010