• 마이크로전자및패키징학회지
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• 제18권4호
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• pp.1-9
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• 2011

Understanding the void characterization in the solder joints has become more important because of the application of lead free solder materials and its reliability in electronic packaging technology. According to the JEDEC 217 standard, it describes void types formed in the solder joints, and divides into some categories depending on the void position and formation cause. Based on the previous papers and the standards related to the void, reliability of the BGA solder joints is determined by the size of void, as well as the location of void inside the BGA solder ball. Prior to reflow soldering process, OSP(organic surface preservative) finished Cu electrode was exposed under $85^{\circ}C$/60%RH(relative humidity) for 168 h. Voids induced by the exposure of $85^{\circ}C$/60%RH became larger and bigger with increasing aging times. The void position has more influence on mechanical strength property than the amount of void growth does.

• 마이크로전자및패키징학회지
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• 제15권1호
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• pp.33-37
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• 2008

Kirkendall void는 전해도금 Cu/Sn-Ag 솔더 접합부에서 형성되었으며 Cu 도금욕에 함유되는 첨가제에 의존한다. 첨가제로 사용된 SPS의 함량의 증가와 함께 $150^{\circ}C$에서 열처리 후 많은 양의 Kirkendall void가 $Cu/Cu_3Sn$ 계면에 존재하였다. AES 분석은 void 표면에 S가 편석되어 있음을 보여주었다. $Cu/Cu_3Sn$ 계면을 따라 파괴된 시편에서 Cu, Sn, S peak만 검출되었고 AES 깊이 프로파일에서 S는 급격하게 감소하였다. $Cu/Cu_3Sn$ 계면에서 S 편석은 계면에너지를 낮추고 Kirkendall void 핵생성을 위한 에너지장벽을 감소시킨다. 낙하충격시험은 SPS를 사용하여 도금된 Cu의 경우 Kirkendall void가 형성된 $Cu/Cu_3Sn$ 계면에서 파괴가 진행되고 급격하게 신뢰성이 감소됨을 보였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1993년도 추계학술대회 논문집
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• pp.49-54
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• 1993

This paper discusses the reliability of solder joints of electronic devices on printed circuit board. Solder application is usually done by screen printing method for the bonding between outer leads of devices and thick film(Ag/Pd) pattern on Hybrid IC as wel1 as Cu lands on PCB. As result of thermal stresses generated at the solder joints due to the differences of thermal expansion coefficients between packge body and PCB, Micro cracking often occurs due to thermal fatigue failure at solder joints. The initiation and the propagate of solder joint crack depends on the environmental conditions, such as storage temperature and thermal cycling. The principal mechanisms of the cracking pheno- mana are the formation of kirkendal void caused by the differences in diffusion rate of materials, ant the thermal fatigue effect due to the differences of thermal expansion coefficient between package body and PCB. Finally, This paper experimentally shows a way to supress solder joints cracks by using low-${\alpha}$ PCB and the packages with thin lead frame, and investigates the phenomena of diffusion near the bonding interfaces.

• 반도체디스플레이기술학회지
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• 제20권2호
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• pp.126-130
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• 2021

The ball grid array is one of the packaging methods that used in high density printed circuit board. Solder void defects caused by voids in the solder ball during the BGA process do not directly affect the reliability of the product, but it may accelerate the aging of the device on the PCB layer or interface surface depending on its size or location. Void inspection is important because it is related in yields with products. The most important process in the optical inspection of solder void is the segmentation process of solder and void. However, there are several segmentation algorithms for the vision inspection, it is impossible to inspect all of images ideally. When X-Ray images with poor contrast and high level of noise become difficult to perform image processing for vision inspection in terms of software programming. This paper suggests the solution to deal with the suggested problem by means of using Mask R-CNN instead of digital image processing algorithm. Mask R-CNN model can be trained with images pre-processed to increase contrast or alleviate noises. With this process, it provides more efficient system about complex object segmentation than conventional system.

• 한국공작기계학회논문집
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• 제16권5호
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• pp.151-156
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• 2007

In this paper, the creep characteristics of lead and lead-free solder joint were investigated using the QFP(Quad Flat Package) creep test. Two kind of solder pastes(Sn-3Ag-0.5Cu, Sn-0.2Sb-0.4Ag-37.4Pb) were applied to the QFP solder joints and each specimen was checked the external and internal failures(i.e., wetting failure, void, pin hole, poor-heel fillet) by digital microscope and X-ray inspection. The creep test was conducted at the temperatures of $100^{\circ}C$ and $130^{\circ}C$ under the load of 15$\sim$20% of average pull strength in solder joints. The creep characteristics of each solder joints were compared using the creep strain-time curve and creep strain rate-stress curves. Through the comparison, the Sn-3Ag-0.5Cu solder joints have higher creep resistance than that of Sn-0.3Sb-0.4Ag-37.4Pb. Also, the grain boundary sliding in the fracture surface and the necking of solder joint were observed by FE-SEM.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2004년도 ISMP Pb-free solders and the PCB technologies related to Pb-free solders
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• pp.1-26
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• 2004

The implementation of Pb-free solder technology is making good progress in electronic industry. Further understanding on fundamental issues on Pb-free solders/processes is required to reduce reliability risk factors of Pb-free solder joints. Several reliability issues including thermal fatigue, impact reliability, IMC growth, spalling, void formation are reviewed for Pb-free solder joints. Several applications of Pb-free technology are discussed, such as Pb-free, CBGA, CuCGA, flip chips, and wafer bumping by IMS.

• 마이크로전자및패키징학회지
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• 제24권2호
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• pp.23-27
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• 2017

본 논문에서는 고온히터의 주 고장 원인이 되는 단자대 솔더 접합부의 손상 원인을 파악하여 사용 수명을 예측하는 방법을 제시하였다. 고온 히터 사용에 따르는 온도 스트레스로 인한 단자대 솔더 접합부의 영향을 알아보기 위해 동일한 부하 조건을 재현할 수 있는 고온히터 시편을 제작하였다. 고온히터 단자대의 단락은 주로 솔더접합부 내의 금속간 화합물이나 void로 인한 crack발생에서 기인한다. 가속시험을 통한 고장 재현을 위해 고온히터 시편을 $170^{\circ}C$의 오븐에서 장시간 동안 노출시키며 솔더 내부의 금속간 화합물 조성과 void의 변화를 측정하였다. 솔더 내의 금속간 화합물 층의 변화를 확인하기 위해서 주사전자현미경을 이용한 단면 분석을 시행하였고, 시편의 온도 스트레스로 인한 void 변화를 측정하기 위해 저항분광법을 이용한 특정 기준 주파수와 위상에 대한 신호를 실시간으로 측정하는 동시에 microCT를 이용하여 void 분율을 간헐적으로 관찰하였다. 시험결과 고온 노출 시간이 증가함에 따라 솔더 내부의 void의 분율이 증가하는 것을 확인하였으며 위상차 변화와 높은 상관관계가 있음을 확인하였다. 이 상관관계를 통해 온도 스트레스에 노출된 고온히터의 수명을 비파괴적으로 예측할 수 있음을 제시하였다.

• Advances in materials Research
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• 제1권1호
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• pp.83-92
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• 2012

The effect of under-bump-metallization (UBM) on electromigration was investigated at temperatures ranging from $135^{\circ}C$ to $165^{\circ}C$. The UBM structures were examined: 5-${\mu}m$-Cu/3-${\mu}m$-Ni and $5{\mu}m$ Cu. Experimental results show that the solder joint with the Cu/Ni UBM has a longer electromigration lifetime than the solder joint with the Cu UBM. Three important parameters were analyzed to explain the difference in failure time, including maximum current density, hot-spot temperature, and electromigration activation energy. The simulation and experimental results illustrate that the addition 3-${\mu}m$-Ni layer is able to reduce the maximum current density and hot-spot temperature in solder, resulting in a longer electromigration lifetime. In addition, the Ni layer changes the electromigration failure mode. With the $5{\mu}m$ Cu UBM, dissolution of Cu layer and formation of $Cu_6Sn_5$ intermetallic compounds are responsible for the electromigration failure in the joint. Yet, the failure mode changes to void formation in the interface of $Ni_3Sn_4$ and the solder for the joint with the Cu/Ni UBM. The measured activation energy is 0.85 eV and 1.06 eV for the joint with the Cu/Ni and the Cu UBM, respectively.

• 마이크로전자및패키징학회지
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• 제31권1호
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• pp.35-42
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• 2024

최근 반도체 칩의 소형화 및 고집적화에 따라 미세 피치에 의한 범프 브리지 (bump bridge) 현상이 문제점으로 주목받고 있다. 이에 따라 범프 브리지 현상을 최소화할 수 있는 Cu pillar bump가 미세 피치에 대응하기 위해 반도체 패키지 산업에서 널리 적용되고 있다. 고온의 환경에 노출될 경우, 접합부 계면에 형성되는 금속간화합물(Intermetallic compound, IMC)의 두께가 증가함과 동시에 일부 IMC/Cu 및 IMC 계면 내부에 Kirkendall void가 형성되어 성장하게 된다. IMC의 과도한 성장과 Kirkendall void의 형성 및 성장은 접합부에 대한 기계적 신뢰성을 약화시키기 때문에 이를 제어하는 것이 중요하다. 따라서, 본 연구에서는 CS(Cu+ Sn-1.8Ag Solder) 구조 Cu pillar bump의 등온 시효 처리에 따른 접합부 특성 평가가 수행되었으며 그 결과가 보고되었다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 International Symposium
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• pp.165-172
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• 2003

Wafer-level packaging technology has become established with increase of demands for miniaturizing and realizing lightweight electronic devices evolution. This packaging technology enables the smallest footprint of packaged chip. Various structures and processes has been proposed and manufactured currently, and products taking advantages of wafer-level package come onto the market. The package enables mounting semiconductor chip on print circuit board as is a case with conventional die-level CSP's with BGA solder bumps. Bumping technology is also advancing in both lead-free solder alternative and wafer-level processing such as stencil printing using solder paste. It is known lead-free solder bump formation by stencil printing process tend to form voids in the re-flowed bump. From the result of FEM analysis, it has been found that the strain in solder joints with voids are not always larger than those of without voids. In this paper, characteristics of wafer-level package and effect of void in solder bump on its reliability will be discussed.