• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1992.05a
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• pp.105-109
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• 1992

ITO film, 1500${\AA}$ of thickness, onto glass and p-InP wafer was prepared by e-beam evaporator. The bet ITO film had the resistivity 5.3${\times}$10$\^$-3/ $\Omega$-cm, the concentration 6.5${\times}$10$\^$20/cm$\^$-3/, the transmittance above 80%, and the optical energy gap about 3.5eV. The higher pressure of injected oxygen, the less reverse bias saturation current and the more open circuit voltage. Under the optimum evaporation conditions, the efficiency was 7.19% and the series resistance, and the shunt resistance were respectively 8.5%, 3${\alpha}$, and 26K$\Omega$. The interdependence between activation energy and pre-exponential factor was found. We found he surface of the p-InP became n-type and consquently supposed that the buried homojunction formation, that is, n+-ITO/n-InP/p-InP was caused by Sn diffusion or loss of phosphorus in the interface layer.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.20 no.1
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• pp.7-11
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• 2010

The reduction of optical losses in mono-crystalline silicon solar cell by surface texturing is a critical step to improve the overall cell efficiency. In this study, we have changed the sub-micrometer structure on the micrometer pyramidal structure by 2-step texturing. The Ag particles were coated on the micrometer pyramid surface in $AgNO_3$ solution, and then the etching with hydrogen fluoride and hydrogen peroxide created even smaller nano-pyramids in these pyramids. As a result, we observed that the changes of size and thickness of nano structure on pyramidal surface were determined by $AgNO_3$ concentration and etching time. Using 2-step texturing, the surface of wafers is etched to resemble the rough surface of a lotus leaf. Lotus surface can reduce average reflectance from 10% to below 3%. This reflectance is less than conventional textured wafer including anti-reflection coating.

• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.3
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• pp.42-51
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• 1981

Boron was predeposited into p (100) Si wafer at 94$0^{\circ}C$ for 60minutes to make the back surface field. High tempreature diffusion process at 1145$^{\circ}C$ for 3 hours was immediately followed without removing boron glass to obtain high surface concentration Back boron was annealed at 110$0^{\circ}C$ for 40minutes after boron glass was removed. N+ layer was formed by predepositing with POCI3 source at 90$0^{\circ}C$ for 7~15 minutes and annealed at 80$0^{\circ}C$ for 60min1es under dry Of ambient. The triple metal layers were made by evaporating Ti, Pd, Ag in that order onto front and back of diffused wafer to form the front grid and back electrode respectively. Silver was electroplated on front and back to increase the metal thickness form 1~2$\mu$m to 3~4$\mu$m and the metal electrodes are alloyed in N2 /H2 ambient at 55$0^{\circ}C$ and followed by silicon nitride antireflection film deposition process. Under artificial illumination of 100mW/$\textrm{cm}^2$ fabricated N+PP+ cells showed typically the open circuit voltage of 0.59V and short circuit current of 103 mA with fill factor of 0.80 from the whole cell area of 3.36$\textrm{cm}^2$. These numbers can be used to get the actual total area(active area) conversion efficiency of 14.4%(16.2%) which has been improved from the provious N+P cell with 11% total area efficiency by adding P+ back.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.406-406
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• 2016

To get high efficiency n-type crystalline silicon solar cells, passivation is one of the key factor. Tunnel oxide (SiO2) reduce surface recombination as a passivation layer and it does not constrict the majority carrier flow. In this work, the passivation quality enhanced by different chemical solution such as HNO3, H2SO4:H2O2 and DI-water to make thin tunnel oxide layer on n-type crystalline silicon wafer and changes of characteristics by subsequent annealing process and firing process after phosphorus doped amorphous silicon (a-Si:H) deposition. The tunneling of carrier through oxide layer is checked through I-V measurement when the voltage is from -1 V to 1 V and interface state density also be calculated about $1{\times}1012cm-2eV-1$ using MIS (Metal-Insulator-Semiconductor) structure . Tunnel oxide produced by 68 wt% HNO3 for 5 min on $100^{\circ}C$, H2SO4:H2O2 for 5 min on $100^{\circ}C$ and DI-water for 60 min on $95^{\circ}C$. The oxide layer is measured thickness about 1.4~2.2 nm by spectral ellipsometry (SE) and properties as passivation layer by QSSPC (Quasi-Steady-state Photo Conductance). Tunnel oxide layer is capped with phosphorus doped amorphous silicon on both sides and additional annealing process improve lifetime from $3.25{\mu}s$ to $397{\mu}s$ and implied Voc from 544 mV to 690 mV after P-doped a-Si deposition, respectively. It will be expected that amorphous silicon is changed to poly silicon phase. Furthermore, lifetime and implied Voc were recovered by forming gas annealing (FGA) after firing process from $192{\mu}s$ to $786{\mu}s$. It is shown that the tunnel oxide layer is thermally stable.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.6
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• pp.603-609
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• 2022

Passivation quality is mainly governed by epitaxial growth of crystalline silicon wafer surface. Void-rich intrinsic a-Si:H interfacial layer could offer higher resistivity of the c-Si surface and hence a better device efficiency as well. To reduce the resistivity of the contact area, a modification of void-rich intrinsic layer of a-Si:H towards more ordered state with a higher density is adopted by adapting its thickness and reducing its series resistance significantly, but it slightly decreases passivation quality. Higher resistance is not dominated by asymmetric effects like different band offsets for electrons or holes. In this study, multilayer of intrinsic a-Si:H layers were used. The first one with a void-rich was a-Si:H(I₁) and the next one a-SiO_x:H(I₂) were used, where a-SiO_x:H(I₂) had relatively larger band gap of ~2.07 eV than that of a-Si:H (I₁). Using a-SiO_x:H as I₂ layer was expected to increase transparency, which could lead to an easy carrier transport. Also, higher implied voltage than the conventional structure was expected. This means that the a-SiO_x:H could be a promising material for a high-quality passivation of c-Si. In addition, the i-a-SiO_x:H microstructure can help the carrier transportation through tunneling and thermal emission.

• 한국신재생에너지학회:학술대회논문집
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• 2010.06a
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• pp.93.1-93.1
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• 2010

반사방지막은 태양전지 표면에서의 광 반사를 낮춰주며, Si wafer 표면에서의 carrier의 재결합을 줄이는 passivation 역할을 한다. 이를 위한 다양한 물질이 반사방지막으로 사용된다. 단일박막은 passivation 효과가 미미하여 최근 passivation 향상에 도움이 되는 이중구조 반사방지막이 널리 연구되어지고 있다. 하지만 물질이 다양해짐에 따라 공정시간 및 비용이 늘어나고, passivation에 최적화된 물질사용이 필수적으로 요구되는 단점이 있다. 따라서 본 연구에서는 기존에 passivation 효과가 뛰어나다고 알려진 SiNx의 굴절률 가변을 통하여 이중구조를 갖는 박막을 반사방지막으로 이용하여 그 특성을 비교, 분석하였다. SiNx 이중반사방지막은 0.8 Torr~1 Torr의 압력에서 $450^{\circ}C$의 기판온도로 PECVD를 이용하여 증착되었으며 이때의 plasma power는 180mW/$cm^2$으로 고정 하였다. 굴절률 1.9 및 2.3을 갖는 가스 조성비를 이용하여 각 layer의 두께를 20/60nm, 30/50nm, 40/40nm로 가변하였다. 샘플 제작 후 Sun-Voc 측정을 통하여 implied Voc 및 효율을 측정하였다. 단일반사방지막을 사용한 샘플의 경우 608mV의 implied Voc가 측정되었으며, FF는 82.8%, 효율은 17.6%로 측정되었다. 가장 우수한 특성을 나타낸 20/60nm의 두께로 증착된 샘플의 경우 implied Voc는 625mV, FF는 84.1%, 효율은 18.3%로 우수한 결과를 나타내었다. 반사도 측정 결과 단일반사방지막은 2.27%로 높았으나 SiNx 이중구조를 이용한 반사방지막은 1.67%로 낮은 값을 확인 하여 이중구조의 반사방지막이 반사도 저감 및 passivation 효과 향상에 도움이 되는 것을 확인할 수 있었다.

• Korean Journal of Materials Research
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• v.26 no.8
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• pp.401-405
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• 2016

The cobalt silicides were investigated for employment as a catalytic layer for a DSSC. Using an E-gun evaporation process, we prepared a sample of 100 nm-thick cobalt on a p-type Si (100) wafer. To form cobalt silicides, the samples were annealed at temperatures of $300^{\circ}C$, $500^{\circ}C$, and $700^{\circ}C$ for 30 minutes in a vacuum. Four-point probe, XRD, FE-SEM, and CV analyses were used to determine the sheet resistance, phase, microstructure, and catalytic activity of the cobalt silicides. To confirm the corrosion stability, we also checked the microstructure change of the cobalt silicides after dipping into iodide electrolyte. Through the sheet resistance and XRD results, we determined that $Co_2Si$, CoSi, and $CoSi_2$ were formed successfully by annealing at $300^{\circ}C$, $500^{\circ}C$, and $700^{\circ}C$, respectively. The microstructure analysis results showed that all the cobalt silicides were formed uniformly, and CoSi and $CoSi_2$ layers were very stable even after dipping in the iodide electrolyte. The CV result showed that CoSi and $CoSi_2$ exhibit catalytic activities 67 % and 54 % that of Pt. Our results for $Co_2Si$, CoSi, and $CoSi_2$ revealed that CoSi and $CoSi_2$ could be employed as catalyst for a DSSC.

• 한국신재생에너지학회:학술대회논문집
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• 2009.06a
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• pp.89-89
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• 2009

높은 소수반송자 수명(life-time)을 가지는 고품위 실리콘 기판은 고효율 실리콘 이종접합 태양전지 제작을 위한 중요 요소 기술 중 하나이다. 본 연구에서는 n-type c-Si 기판을 이용한 고효율 실리콘 이종접합 태양전지제작을 위해 hot water oxidation(HWO) 공정을 이용하여 고품위 실리콘 기판을 제작하였다. 실리콘 기판의 특성 분석은 Qusi-steady state photoconductance (QSSPC)를 이용하여 소수반송자 수명을 측정하였으며, 기판의 면저항 및 wetting angle을 측정하여 공정에 따른 특성변화를 분석하였다. Saw damage etching 된 기판을 웨이퍼 표면으로부터 particle, 금속 불순물, 유기물 등의 오염을 제거하기 위해 $60{\sim}85^{\circ}C$로 가열된 Ammonia수, 과산화수소수($NH_4OH/H_2O_2/H_2O$), 염산 과산화수소수($HCL/H_2O_2/H_2O$) 및 실온 희석불산(DHF) 중에 기판을 각각 10분 정도씩 침적하여, 각각의 약액 처리 후에 매회 10분 정도씩 순수(DI water)에서 rinse하여 RCA 세정을 진행한 후 HWO 공정을 통해 기판 표면에 얇은 산화막 을 형성시켜 패시베이션 해주었다. HF를 이용하여 자연산화막을 제거시 HWO 공정을 거친 기판은 매끄러운 표면과 패시베이션 영향으로 기판의 소수 반송자 수명이 증가하며, 태양전지 제작시 접촉저항을 감소시켜 효율을 증가 시킬수 있다. HWO 공정은 반응조 안의 DI water 온도와 반응 시간에 따라 life-time을 측정하여 진행하였으며, 이후 PE-CVD법으로 증착된 a-Si:H layer 및 투명전도 산화막, 금속전극을 증착하여 실리콘 이종접합 태양전지를 제작하였다.

• 한국신재생에너지학회:학술대회논문집
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• 2011.05a
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• pp.107.1-107.1
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• 2011

현재 상용으로 많이 사용되는 p-type 태양전지는 Dopant로 사용된 Boron이 $O_2$와 결합하면서 Light induced degradation이 발생하여 태양 전지 효율의 감소를 불러일으키는 단점이 있다. 이러한 문제를 해결하기 위하여 여러 가지 방법들이 제시되었는데 일반적으로 n-type wafer를 이용함으로써 Light induced degradation을 해결하는 방법이 주로 사용된다. n-type 태양전지를 제조함에 있어서 보다 높은 효율을 달성하기 위하여 태양전지 후면 구조에 local contact 개념을 도입하여 rear local emitter를 형성함으로써 전체적인 효율 증가를 도모하였다. 이러한 local contact을 제조하기 위해서는 전기적으로 구조적으로 고려할 사항들이 여러 가지 존재한다. 따라서 우리는 이러한 고려 사항들을 실험적인 방법으로 결정하는 것이 아니라, 정교한 변수 통제를 이용한 시뮬레이션으로 최종적인 효율 상승을 가져오는 조건을 찾으려고 한다. 이때 사용될 수 있는 시뮬레이션은 여러 가지 종류가 존재하는데 우선 상용 태양전지의 해석에 가장 많이 사용되는 PC1D프로그램이 있다. 그러나 PC1D의 경우에는 1차원의 해석만 가능하기 때문에 local contact의 2차원 이상의 구조 변화에 따른 최종적인 효율을 계산하는데 무리가 따르게 된다. 따라서 2차원 이상의 형상에 대한 분석이 가능한 프로그램을 이용하여 실제 셀에서 일어나는 현상을 더 정밀하게 모사함으로써 local contact에서 일어나는 전기적, 구조적 변화가 최종적인 효율에 어떻게 영향을 미치는지를 파악해볼 것이며, 어떤 구조를 선택하였을 때 가장 높은 효율을 달성할 수 있는지 알아보려고 한다.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.188.1-188.1
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• 2014

Aluminum is widely used as a material for electrode on silicon based devices. Especially, aluminum films are used as backside and front-side electrodes in silicon quantum dot (QD) solar cells. In this point, the diffusion of aluminum is very important for the enhancement of power conversion efficiency by improvement of contact property. Aluminum was deposited on a Si (100) wafer and a Si QD layer by ion beam sputter system with a DC ion gun. The Si QD layer was fabricated by $1100^{\circ}C$ annealing of the $SiO_2/SiO_1$ multilayer film grown by ion beam sputtering deposition. Cs ion beam with a low energy and a grazing incidence angle was used in SIMS depth profiling analysis to obtain high depth resolution. Diffusion behavior of aluminum in the Al/Si and Al/Si QD interfaces was investigated by secondary ion mass spectrometry (SIMS) as a function of heat treatment temperature. It was found that aluminum is diffused into Si substrate at $450^{\circ}C$. In this presentation, the effect of heat treatment temperature and Si nitride diffusion barrier on the diffusion of Al will be discussed.