• The Transactions of the Korea Information Processing Society
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• v.5 no.3
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• pp.620-632
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• 1998

This paper introduces a new teehniquc for reducing the compulsory misses of software-managed TLBs by prefetching necessary TLB entries before being used. This technique is not inherently limited to specific applications. The key of this scheme is to perform the prefetch operations to update the TLB entries before first accesses so that TLB misses can be avoided. For the identifications of the prefctch pages, the new classification is introduced, which is based 0n the view of an object code execution. Then, the algorithms and the implementation technique arc described. Using a quantitative analysis, the proposed scheme is evaluated to prove that it is a useful technique for the perronnall~~ ~nhan~"ment of the S/W managed TLBs. in addition, it is discussed that reducing the miss rate by the prefeteh scheme reduces the total miss penalty and bus traffics in S/W-managed TLBs.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.5
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• pp.350-354
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• 2009

To optimize the performance of software programs, it is important to know certain hardware parameters such as the CPU speed, the cache size, the number of TLB entries, and the parameters of the memory subsystem. There exist several ways to obtain the values of various hardware parameters. Firstly. the values can be taken from the hardware manual. Secondly, the parameters can be obtained by calling functions provided by the operating systems. Finally, hardware detection programs can find the desired values. Such programs are usually executed on PC or server systems and report the CPU speed, the cache size, the number of TLB entries, and so on. However, they do not sufficiently detect the parameters of one of the most important parts of the computer concerning performance, namely the memory bank layout in the memory subsystem. In this paper, we present an algorithm to detect the memory bank parameters. We run an implementation of our algorithm on various embedded systems and compare the detected values with the real hardware parameters. The results show that the presented algorithm detects the cache size, the number of TLB entries, and the memory bank layout with high accuracy.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.94-100
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• 2008

It is necessary to develop the flash memory system software FTL(Flash Translation Layer) which is used in mobile storage like Compact Flash memory. In this paper, we design the FTL using clustered hash table and two phase software caching method to translate logical address into physical address fastly. The experimental results show that the address translation performance of CFTL is 13.3% higher than that of NFTL and 8% higher than that of AFTL, and the memory usage of CFTL is 75% smaller than that of AFTL.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.1
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• pp.68-80
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• 2000

The modern software technology toward modularization has changed the cache accessing behavior dramatically. Many modern operating systems are also departing from the past monolithic structure toward the highly modularized structure referred to as microkernel. Microkernel-based operating systems are more portable and extensible, but are likely to have worse performance. This paper quantitatively analyzes the effect of microkernel structure on cache memory to identify the primary factor for its performance degradation. Through the experiment performed on a Intel Pentium Pro processor platform, we found that the microkernel structure suffers from remarkably higher misses for L1, L2 cache and TLB than the monolithic one does. We also found that the performance of a microkernel is more dependent on the efficiency of cache memory than IPC. Finally, we found that these results come from the effect of frequent context switches mainly caused by the structural feature of a microkernel.

• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.3
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• pp.190-200
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• 2011

Android platform provides a content provider and a cursor mechanism to access the internal SQLite engine. Content providers not only store and retrieve data but also make it accessible to applications. Applications can only share data through content provider, since there's no common storage area that Android packages can access. Cursor is an interface that provides random read-write access to the result set returned by a database query. However, this cursor possesses two major limitations. First, a cursor does not support a join clause among cursors, since the cursor can only access a single table in the content provider. Second, the cursor is not capable of creating user-customized field in the predefined content providers. In this paper, we propose the unified cursor architecture that merges several cursors into a single virtual cursor. Cursor translation look-aside buffer (TLB), column windowing mechanism and virtual data management are the three major techniques we have adopted to implement our structure. And we also propose a delayed synchronization method between an application and a proposed unified cursor. An application can create a user-customized field and sort multiple tables using a unified cursor on Android platform.