• Title/Summary/Keyword: Software PLL

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Design of Analog ASIC for high frequency Phase Lock Loop (IEEE1394 S800대응 고주파 PLL ASIC 설계)

  • Kim, Y.W.;Lee, H.B.;Cho, G.O.;Han, D.I.;Lee, K.W.
    • Proceedings of the KIEE Conference
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    • 1998.11b
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    • pp.582-584
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    • 1998
  • IEEE1394 is an international standard that will integrate entertainment, communication, and computing electronics into consumer multimedia. IEEE1394 is a hardware and software for transporting data at 100,200, or 400Mbps. There are efforts to create speed improvements to 800 and muti-Gigabit speed s. An 980Mhz frequency synthesizer is proposed for high speed transport and designed by a 0.35um CMOS process.

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Development of FPGA-based Programmable Timing Controller

  • Cho, Soung-Moon;Jeon, Jae-Wook
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.1016-1021
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    • 2003
  • The overall size of electronic product is becoming small according to development of technology. Accordingly it is difficult to inspect these small components by human eyes. So, an automation system for inspecting them has been used. The existing system put microprocessor or Programmable Logic Controller (PLC) use. The structure of microprocessor-based controller and PLC use basically composed of memory devices such as ROM, RAM and I/O ports. Accordingly, the system is not only becomes complicated and enlarged but also higher price. In this paper, we implement FPGA-based One-chip Programmable Timing Controller for Inspecting Small components to resolve above problems and design the high performance controller by using VHDL. With fast development, the FPGA of high capacity that can have memory and PLL have been introduced. By using the high-capacity FPGA, the peripherals of the existent controller, such as memory, I/O ports can be implemented in one FPGA. By doing this, because the complicated system can be simplified, the noise and power dissipation problems can be minimized and it can have the advantage in price. Since the proposed controller is organized to have internal register, counter, and software routines for generating timing signals, users do not have to problem the details about timing signals and need to only send some values about an inspection system through an RS232C port. By selecting theses values appropriate for a given inspection system, desired timing signals can be generated.

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Implementation and Control of AC-DC-AC Power Converter in a Grid-Connected Variable Speed Wind Turbine System with Synchronous Generator (동기기를 사용한 계통연계형 가변속 풍력발전 시스템의 AC-DC-AC 컨버터 구현 및 제어)

  • Song Seung-Ho;Kim Sung-Ju;Hahm Nyon-Kun
    • The Transactions of the Korean Institute of Electrical Engineers B
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    • v.54 no.12
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    • pp.609-615
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    • 2005
  • A 30kW electrical power conversion system is developed for a variable speed wind turbine. In the wind energy conversion system(WECS) a synchronous generator with field current excitation converts the mechanical energy into electrical energy. As the voltage and the frequency of the generator output vary according to the wind speed, a 6-bridge diode rectifier and a PWM boost chopper is utilized as an ac-dc converter maintaining the constant dc-link voltage with only single switch control. An input current control algorithm for maximum power generation during the variable speed operation is proposed without any usage of speed sensor. Grid connection type PWM inverter converts dc input power to ac output currents into the grid. The active power to the grid is controlled by q-axis current and the reactive power is controlled by d-axis current with appropriate decoupling. The phase angle of utility voltage is detected using software PLL(Phased Locked Loop) in d-q synchronous reference frame. Experimental results from the test of 30kW prototype wind turbine system show that the generator power can be controlled effectively during the variable speed operation without any speed sensor.

Modelling and Performance Analysis of UPQC with Digital Kalman Control Algorithm under Unbalanced Distorted Source Voltage conditions

  • Kumar, Venkateshv;Ramachandran, Rajeswari
    • Journal of Power Electronics
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    • v.18 no.6
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    • pp.1830-1843
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    • 2018
  • In this paper, the generation of a reference current and voltage signal based on a Kalman filter is offered for a 3-phase 4wire UPQC (Unified Power Quality Conditioner). The performance of the UPQC is improved with source voltages that are distorted due to harmonic components. Despite harmonic and frequency variations, the Kalman filter is capable enough to determine the amplitude and the phase angle of load currents and source voltages. The calculation of the first state is sufficient to identify the fundamental components of the current, voltage and angle. Therefore, the Kalman state estimator is fast and simple. A Kalman based control strategy is proposed and implemented for a UPQC in a distribution system. The performance of the proposed control strategy is assessed for all possible source conditions with varying nonlinear and linear loads. The functioning of the proposed control algorithm with a UPQC is scrutinized and validated through simulations employing MATLAB/Simulink software. Using a FPGA SPATRAN 3A DSP board, the proposed algorithm is developed and implemented. A small-scale laboratory prototype is built to verify the simulation results. The stated control scheme for the UPQC reduces the following issues, voltage sags, voltage swells, harmonic distortions (voltage and current), unbalanced supply voltage and unbalanced power factor under dynamic and steady-state operating conditions.

The Design Method of GNSS Signal Using the Analysis Result of Receiver Performance (수신 성능 분석을 이용한 위성항법 신호 설계 방안)

  • Jin, Mi-Hyun;Choi, Heon-Ho;Kim, Kap-Jin;Park, Chan-Sik;Ahn, Jae-Min;Lee, Sang-Jeong
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.37 no.6C
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    • pp.502-511
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    • 2012
  • As the importance of GNSS system increases, the necessity of independent system is increased also. When the independent GNSS system is required, GNSS signal design is necessary with requirement definition. This paper suggests the design method of GNSS signal using the analysis result of receiver performance. First, the candidates are defined based on the design elements. Then the receiver performance of the candidates is analyzed based on the performance evaluation parameters. The weights of performance evaluation parameter are defined in order to consider the receiver performance in a various aspects. Finally, the calculation of normalized performance evaluation parameters and weights are derived to obtain the compared value for signal selection. Spreading code, modulation method and carrier frequency are considered as design parameters. Also, correlation width, DLL PLL thermal noise jitter, frequency bandwidth and side lobe peak ratio are considered as performance evaluation parameters. And positioning performance, robustness to noise, bandwidth efficiency are considered as the performance aspects. This paper analyzes the performance of each candidate using software based simulator and suggest the method to compare objectively the performance of each candidates.

Synchronization Algorithm and Demodulation using the Phase Transition Detection in the DSP based MPSK Receiver (DSP 기반 MPSK 수신기에서 위상천이 검출을 이용한 동기 알고리즘과 복조)

  • Lee Jun-Seo;Maing Jun-Ho;Ryu Heung-Gyoon;Park Cheol-Sun;Jang Won
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.15 no.10 s.89
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    • pp.952-960
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    • 2004
  • PSK(Phase Shift Keying) is useful because of the power and spectral efficient modulation. In this paper, no additional hardware will be needed to support various transmit mode in the suggested DSP scheme. We design and implement the synchronization algorithm for M-ary PSK(M=2, 4) demodulator based on DSP scheme, instead of complex analog PSK demodulator. TMS320C6203 is used as DSP. We check the all kinds of waveforms via the graph view window after software programming the emulation on the DSP tool. The result of implementation proves that demodulator using the suggested algorithm has equal performance with demodulator using analog circuits.

Phase Jitter Analysis of Overlapped Signals for All-to-All TWSTFT Operation

  • Juhyun Lee;Ju-Ik Oh;Joon Hyo Rhee;Gyeong Won Choi;Young Kyu Lee;Jong Koo Lee;Sung-hoon Yang
    • Journal of Positioning, Navigation, and Timing
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    • v.12 no.3
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    • pp.245-255
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    • 2023
  • Time comparison techniques are necessary for generating and keeping Coordinated Universal Time (UTC) and distributing standard time clocks. Global Navigation Satellite System (GNSS) Common View, GNSS All-in-View, Two-Way Satellite Time and Frequency Transfer (TWSTFT), Very Long Baseline Interferometry (VLBI), optical fiber, and Network Time Protocol (NTP) based methods have been used for time comparison. In these methods, GNSS based time comparison techniques are widely used for time synchronization in critical national infrastructures and in common areas of application such as finance, military, and wireless communication. However, GNSS-based time comparison techniques are vulnerable to jamming or interference environments and it is difficult to respond to GNSS signal disconnection according to the international situation. In response, in this paper, Code-Division Multiple Access (CDMA) based All-to-All TWSTFT operation method is proposed. A software-based simulation platform also was designed for performance analysis in multi-TWSTFT signal environments. Furthermore, code and carrier measurement jitters were calculated in multi-signal environments using the designed simulation platform. By using the technique proposed in this paper, it is anticipated that the TWSTFT-based time comparison method will be used in various fields and satisfy high-performance requirements such as those of a GNSS master station and power plant network reference station.